Gallium nitride material devices including an electrode-defining layer and methods of forming the same
Gallium nitride material devices and methods of forming the same are provided. The devices include an electrode-defining layer. The electrode-defining layer typically has a via formed therein in which an electrode is formed (at least in part). Thus, the via defines (at least in part) dimensions of the electrode. In some cases, the electrode-defining layer is a passivating layer that is formed on a gallium nitride material region.
1 . A semiconductor structure comprising:
a gallium nitride material region;
an electrode-defining layer formed over the gallium nitride material region and including a via formed therein, a cross-sectional area at a top of the via being greater than a cross-sectional area at a bottom of the via; and
an electrode formed on the gallium nitride material region and in the via, wherein the electrode length is defined at the bottom of the via.
2 . The semiconductor structure of claim 1 , wherein the electrode is a gate electrode.
3 . The semiconductor structure of claim 2 , further comprising a source electrode formed on the gallium nitride material region and a drain electrode formed on the gallium nitride material region.
4 . The semiconductor structure of claim 3 , wherein the gate electrode extends over a portion of the top surface of the electrode-defining layer a distance, in a direction of the drain electrode, of between about 2% and about 60% of a distance between the gate electrode and the drain electrode.
5 . The semiconductor structure of claim 18 , wherein the gate electrode extends over a portion of the top surface of the electrode-defining layer a distance in a direction of the drain electrode greater than a distance in a direction of the source electrode.
6 . The semiconductor structure of claim 19 , wherein the gate electrode extends over a portion of the top surface of the electrode-defining layer a distance, in a direction of the source electrode, of less than 50% the distance the gate electrode extends over the electrode-defining layer in the direction of the drain electrode.
7 . The semiconductor structure of claim 1 , wherein the ratio of the electrode length to a cross-sectional dimension at the top of the via is between about 0.50 and 0.95.
8 . The semiconductor structure of claim 1 , wherein the ratio of the electrode length to a cross-sectional dimension at the top of the via is between about 0.75 and 0.90.
9 . The semiconductor structure of claim 1 , wherein the electrode is a Schottky contact.
10 . The semiconductor structure of claim 9 , further comprising an ohmic electrode formed on the gallium nitride material region.
11 . A Schottky diode comprising:
a gallium nitride material region;
an electrode-defining layer formed over the gallium nitride material region and including a via formed therein, a cross-sectional area at a top of the via being greater than a cross-sectional area at a bottom of the via, wherein a sidewall of the via extends upward from the bottom of the via at an angle between about 5 degrees and about 85 degrees and downward from the top of the via at an angle between about 90 degrees and about 160 degrees;
a Schottky electrode formed on the gallium nitride material region and in the via, wherein the electrode length is defined at the bottom of the via; and
an ohmic electrode formed on the gallium nitride material region.
12 . A method of forming a semiconductor structure comprising:
forming an electrode-defining layer on a gallium nitride material region;
forming a via in the electrode-defining layer such that a cross-sectional dimension at a top of the via is greater than a cross-sectional dimension at a bottom of the via;
forming an electrode on the gallium nitride material region and in the via, wherein a length of the electrode is defined by the bottom of the via.
13 . The method of claim 12 , comprising forming the via in a plasma etching step.
14 . The method of claim 13 , wherein pressure conditions in the plasma are between about 1 mTorr and about 100 mTorr.
15 . The method of claim 12 , wherein the plasma etching step includes maintaining RF power conditions of less than about 50 Watts.
16 . The method of claim 12 , further comprising controlling an angle of a sidewall of the passivating layer to extend upward from a bottom surface of the passivating layer to be between about 5 degrees and about 85 degrees.
17 . A method of forming a transistor comprising:
forming an electrode-defining layer on a gallium nitride material region;
forming a via in the electrode-defining layer such that a cross-sectional dimension at a top of the via is greater than a cross-sectional dimension at a bottom of the via and a sidewall of the via extends upward from the bottom of the via at an angle between about 5 degrees and about 85 degrees and downward from the top of the via at an angle between about 90 degrees and about 160 degrees;
forming a source electrode on the gallium nitride material region;
forming a drain electrode on the gallium nitride material region; and
forming a gate electrode on the gallium nitride material region and in the via, wherein a length of the gate electrode is defined at the bottom of the via and the ratio of the gate electrode length to a cross-sectional dimension at the top of the via is between about 0.50 and 0.95.
18 . A method of forming a Schottky diode comprising:
forming an electrode-defining layer on a gallium nitride material region;
forming a via in the electrode-defining layer such that a cross-sectional dimension at a top of the via is greater than a cross-sectional dimension at a bottom of the via and a sidewall of the via extends upward from the bottom of the via at an angle between about 5 degrees and about 85 degrees and downward from the top of the via at an angle between about 90 degrees and about 160 degrees;
forming an ohmic electrode on the gallium nitride material region; and
forming a Schottky electrode on the gallium nitride material region and in the via, wherein the electrode length is defined at the bottom of the via.