Apparatus and method for generating transistor model
View Patent ↗In a transistor model generating apparatus, a transistor region extracting section extracts a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion layer region, from a mask layout data of a semiconductor integrated circuit. A dividing section sets a division line extending in a direction of a gate length of a transistor to divide the non-rectangular transistor region into a plurality of rectangular transistor regions. A relating section relates the non-rectangular transistor region and the plurality of rectangular transistor regions with the mask layout data. A size calculating section calculates a size data of each of the plurality of rectangular transistor regions. A correction value calculating section calculates a correction value of a diffusion layer length dependency parameter to the plurality of rectangular transistor regions based on the size data. A transistor model registering section registers a transistor model of the transistor for a circuit simulation based on the diffusion layer length dependency parameter and the correction value.
1. A transistor model generating apparatus comprising:
a transistor region extracting section configured to extract a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion layer region, from a mask layout data of a semiconductor integrated circuit;
a dividing section configured to set a division line extending in a direction of a gate length of a transistor to divide said non-rectangular transistor region into a plurality of rectangular transistor regions;
a relating section configured to relate said non-rectangular transistor region and said plurality of rectangular transistor regions with said mask layout data;
a size calculating section configured to calculate a size data of each of said plurality of rectangular transistor regions;
a correction value calculating section configured to calculate a correction value of a diffusion layer length dependency parameter to said plurality of rectangular transistor regions based on said size data; and
a transistor model registering section configured to register a transistor model of said transistor for a circuit simulation based on said diffusion layer length dependency parameter and said correction value.
2. The transistor model generating apparatus according to claim 1 , wherein said extracting section determines that said transistor region is non-rectangular, based on apexes of said transistor region.
3. The transistor model generating apparatus according to claim 1 , wherein a direction of said division line is determined based on positions of apexes of said gate region,
one end of said division line is determined as one associated with a concave section, of apexes on said non-rectangular transistor region, and
the other end of said division line is determined as an intersection of said division line and a frame of said non-rectangular transistor region when said division line is drawn from the one end in the determined direction.
4. The transistor model generating apparatus according to claim 1 , wherein said dividing section allocates said non-rectangular transistor region to a first recognition layer, and allocates each of said plurality of rectangular transistor regions to a second recognition layer.
5. The transistor model generating apparatus according to claim 4 , wherein said dividing section allocates said first and second recognition layers to different unused process layers.
6. The transistor model generating apparatus according to claim 4 , wherein said second recognition layer has a plurality of process layers, and
said plurality of rectangular transistor regions are allocated to said plurality of process layers, respectively.
7. The transistor model generating apparatus according to claim 4 , wherein said transistor model has a first identifier indicating a number of said plurality of rectangular transistor regions.
8. The transistor model generating apparatus according to claim 7 , wherein said transistor model registering section gives a second identifier to said first identifier to indicate a generation order.
9. The transistor model generating apparatus according to claim 1 , wherein said diffusion layer length dependency parameter has a mobility parameter and a threshold voltage parameter, and
said correction value calculating section calculates mobility parameter fmu(DL) from the following equation (1), when a diffusion layer length of an n-th region of said plurality of rectangular transistor regions is DLn and a gate width thereof is Wn, and calculates the threshold voltage parameter fvth(DL) from the following equation (2),
fmu ( DL )= fmu ( DL=DL 1)* W 1/( W 1 +W 2 + . . . +Wn )+ fmu ( DL=DL 2)* W 2/( W 1 +W 2+ . . . + Wn )+ . . . + fmu ( DL=DLn )* Wn /( W 1 +W 2 + . . . +Wn ) (1)
fvth ( DL )= fvth ( DL=DL 1)* W 1/( W 1 +W 2 + . . . + Wn )+ fvth ( DL=DL 2)* W 2/( W 1 +W 2+ . . . + Wn )+ . . . + fvth ( DL=DLn )* Wn /( W 1 +W 2+ . . . + Wn ).
10. A method of generating a transistor model, comprising:
extracting a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion layer region, from a mask layout data of a semiconductor integrated circuit;
dividing said non-rectangular transistor region into a plurality of rectangular transistor regions by a division line extending in a direction of a gate length of a transistor;
relating said non-rectangular transistor region and said plurality of rectangular transistor regions with said mask layout data;
calculating a size data of each of said plurality of rectangular transistor regions;
calculating a correction value of a diffusion layer length dependency parameter to said plurality of rectangular transistor regions based on said size data; and
registering a transistor model of said transistor for a circuit simulation based on said diffusion layer length dependency parameter and said correction value.
11. The method according to claim 10 , wherein said extracting comprises:
determining that said transistor region is non-rectangular, based on apexes of said transistor region.
12. The method according to claim 10 , wherein said dividing comprises:
determining a direction of said division line based on positions of apexes of said gate region;
determining one end of said division line as one associated with a concave section, of apexes on said non-rectangular transistor region; and
drawing said division line from said one end to the other end of said division line as an intersection of said division line and a frame of said non-rectangular transistor region in the determined direction.
13. The method according to claim 10 , wherein said dividing comprises:
allocating said non-rectangular transistor region to a first recognition layer; and
allocating each of said plurality of rectangular transistor regions to a second recognition layer.
14. The method according to claim 13 , wherein said dividing comprises:
allocating said first and second recognition layers to different unused process layers.
15. The method according to claim 13 , wherein said second recognition layer has a plurality of process layers, and
said dividing comprises:
allocating said plurality of rectangular transistor regions to said plurality of process layers, respectively.
16. The method according to claim 13 , wherein said registering comprises:
allocating a first identifier to said transistor model to indicate a number of said plurality of rectangular transistor regions.
17. The method according to claim 16 , wherein said registering comprises:
giving a second identifier to said first identifier to indicate a generation order.
18. The method according to claim 10 , wherein said diffusion layer length dependency parameter has a mobility parameter and a threshold voltage parameter, and
said calculating a correction value comprises:
calculating said correction value calculating section mobility parameter fmu(DL) from the following equation (1), when a diffusion layer length of an n-th region of said plurality of rectangular transistor regions is DLn and a gate width thereof is Wn,
fmu ( DL )= fmu ( DL=DL 1)* W 1/( W 1 +W 2+ . . . + Wn )+ fmu ( DL=DL 2)* W 2/( W 1 +W 2+ . . . + Wn )+ . . . + fmu ( DL=DLn )* Wn /( W 1 +W 2 + . . . +Wn ) (1), and
calculating the threshold voltage parameter fvth(DL) from the following equation (2),
fvth ( DL )= fvth ( DL=DL 1)* W 1/( W 1 +W 2 + . . . +Wn )+ fvth ( DL=DL 2)* W 2/( W 1 +W 2 + . . . +Wn )+ . . . + fvth ( DL=DLn )* Wn /( W 1 +W 2+ . . . + Wn ) (2).
19. A computer-readable software product for realizing a method of generating a transistor model, wherein said method comprises:
extracting a non-rectangular transistor region, in which a gate region is formed above a non-rectangular diffusion layer region, from a mask layout data of a semiconductor integrated circuit;
dividing said non-rectangular transistor region into a plurality of rectangular transistor regions by a division line extending in a direction of a gate length of a transistor;
relating said non-rectangular transistor region and said plurality of rectangular transistor regions with said mask layout data;
calculating a size data of each of said plurality of rectangular transistor regions;
calculating a correction value of a diffusion layer length dependency parameter to said plurality of rectangular transistor regions based on said size data; and
registering a transistor model of said transistor for a circuit simulation based on said diffusion layer length dependency parameter and said correction value.