IP Library Granted Patent US 7,518,481
Granted Patent B2
US 7,518,481 · App. 11/479,236 · Granted Apr 14, 2009

Slotted magnetic material for integrated circuit inductors

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,518,481
App. No.
11/479,236
Granted
Apr 14, 2009
Kind
B2
Abstract

An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.

Claims (32)

1. An inductor comprising:

a plurality of metal lines; and

a slotted magnetic material adjacent to the metal lines, the slotted magnetic material comprising:

a seed layer;

a patterned insulator formed on the seed layer, the patterned insulator defining a plurality of slots; and

a magnetic material formed in the slots and coupled to the seed layer of magnetic material.

2. The inductor of claim 1 further comprising:

an insulator adjacent to the metal lines to insulate the metal lines from the slotted magnetic material.

3. The inductor of claim 1 , the seed layer and magnetic material each comprising an alloy selected from the group of CoZrTa, CoZr, CoZrNb, CoZrMo, FeCoAlN, CoP, FeCoP, CoPW, CoBW, CoPBW, CoHf, CoNb, CoW, CoTi, FeCoN, FeTaN, FeCoBSi, FeNi, CoFeHfO, CoFeSiG, CoZrO, CoFeAlO, or a combination thereof.

4. The inductor of claim 1 further comprising:

another slotted magnetic material adjacent to the metal lines and opposite the slotted magnetic material, the other slotted magnetic material including a plurality of slots.

5. An integrated circuit comprising:

an integrated circuit device; and

an inductor coupled to the integrated circuit device, the inductor including

a plurality of metal lines; and

a slotted magnetic material adjacent to the metal lines, the slotted magnetic material comprising:

a seed layer;

a patterned insulator formed on the seed layer, the patterned insulator defining a plurality of slots;

a magnetic material formed in the slots and coupled to the seed layer of magnetic material, wherein at least a portion of the slotted magnetic material is deposited with electroless plating.

6. The integrated circuit of claim 5 , the inductor further comprising: an insulator adjacent to the metal lines to insulate the metal lines from the slotted magnetic material.

7. The integrated circuit of claim 6 , the slotted magnetic material comprising an alloy selected from the group of CoZrTa, CoZr, CoZrNb, CoZrMo, FeCoAlN, CoP, FeCoP, CoPW, CoBW, CoPBW, CoHf, CoNb, CoW, CoTi, FeCoN, FeTaN, FeCoBSi, FeNi, CoFeHfO, CoFeSiO, CoZrO, CoFeAlO, or a combination thereof.

8. A system comprising:

an off-chip power source; and

an integrated circuit coupled to the off-chip power source, the integrated circuit including one or more voltage converters, each voltage converter including an inductor, the inductor including

a plurality of metal lines; and

a slotted magnetic material adjacent to the metal lines, the slotted magnetic material comprising:

a seed layer;

a patterned insulator formed on the seed layer, the patterned insulator defining a plurality of slots; and

a magnetic material formed in the slots and coupled to the seed layer of magnetic material.

9. The system of claim 8 , the slotted magnetic material comprising an alloy selected from the group of CoZrTa, CoZr, CoZrNb, CoZrMo, FeCoAlN, CoP, FeCoP, CoPW, CoBW, CoPBW, CoHf, CoNb, CoW, CoTi, FeCoN, FeTaN, FeCoBSi, FeNi, CoFeHfO, CoFeSiO, CoZrO, CoFeAlO, or a combination thereof.

10. The system of claim 8 , the insulator selected from the group consisting of SiO 2 , SiN, SiOF, SiOC, polyimide, a photosensitive insulating material, and any other low dielectric constant interlayer dielectric.

11. The system of claim 8 , the integrated circuit further comprising a plurality of integrated circuit devices, each integrated circuit device coupled to the one or more voltage converters, and each voltage converter supplying a different voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2008
From: GARDNER, DONALD; SCHROM, GERHARD; HAZUCHA, PETER; PAILLET, FABRICE; KARNICK, TANAY
To: INTEL CORPORATION
Reel/Frame 020769/0037 →
Continuity (1)
Related Publication 20080001699A1 · Jan 3, 2008