Delay lock loop delay adjusting method and apparatus
View Patent ↗Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is then changed until a preferred delay value, resulting in synchronization, is found. In various embodiments, used of the initial delay value increases the speed, reliability or other beneficial features of the synchronization.
1. A system comprising:
a delay circuit configured to receive a test signal and return a response signal;
a test circuit configured to determine a delay value responsive to a time between sending the test signal and receiving the response signal; and
a delay lock loop configured to determine an initial value for a delay time according to the delay value and to provide a synchronization between a clock and one or more device signals by changing the delay time from this initial value.
2. The system of claim 1 , wherein the delay lock loop is further configured to change the delay time by incrementing the delay time by a predetermined value.
3. The system of claim 1 , wherein the delay lock loop is further configured to change the delay time by decrementing the delay time by a predetermined value.
4. The system of claim 1 , wherein the delay lock loop is further configured to change the delay time by an amount smaller than the initial value of the delay time.
5. The system of claim 1 , wherein the delay lock loop includes a programmable delay circuit.
6. A method comprising:
sending a test signal to a delay circuit and receiving a response signal responsive to the test signal;
determining a delay value according to a propagation time between sending the test signal and receiving the response signal;
communicating the delay value to a delay lock loop configured to provide a synchronization between a clock signal and one or more device signals;
determining a delay time between the clock signal and the one or more device signals using the delay value; and
changing the delay time in the delay lock loop to provide the synchronization between the clock signal and the one or more device signals.
7. The method of claim 6 , wherein the step of changing the delay time further includes using a delay adjustment value.
8. The system of claim 6 , wherein the step of changing the delay time further includes decreasing the delay time.
9. The system of claim 6 , wherein the step of changing the delay time further includes increasing the delay time.
10. The system of claim 6 , wherein the propagation time is responsive to temperature.
11. The system of claim 6 , wherein the propagation time is responsive to a supply voltage.
12. A system comprising:
a test circuit configured to determine a delay value according to the time between sending a test signal and receiving a response signal;
a programmable delay circuit configured to receive the delay value and determine a delay time according to the delay value; and
a timing controller configured to determine a synchronization between a processor and a device in communication with the processor by changing the delay time.
13. The system of claim 12 , further comprising a delay circuit configured to receive the test signal and return the response signal.
14. The system of claim 13 , wherein the device includes the delay circuit.
15. The system of claim 13 , wherein the processor includes the delay circuit.
16. The system of claim 13 , wherein the delay value is responsive to a supply voltage.
17. The system of claim 13 , wherein the delay value is responsive to temperature.
18. A system comprising:
a device configured to communicate with a processor; and
a delay circuit configured to receive a test signal from a controller and return a response signal to the controller, a time between receiving the test signal and sending the response signal being representative of operating characteristics of the device and being configured for determining a synchronization between the processor and the device.
19. The system of claim 18 , wherein the device is coupled to the delay circuit.
20. The system of claim 18 , wherein the device comprises the delay circuit.
21. The system of claim 18 , wherein the operating characteristics of the device include a supply voltage.
22. The system of claim 18 , wherein the operating characteristics of the device include temperature.
23. The system of claim 18 , wherein the operating characteristics of the device are installation or production dependent.
24. The system of claim 18 , wherein the processor is configured to determine a delay time responsive to the time between receiving the response signal and sending the test signal, and to determine the synchronization between the processor and the device by changing the delay time.
25. A method comprising:
receiving a test signal; and
returning a response signal to a controller configured to determine a delay time according to a time between receiving the test signal and sending the response signal and to determine a synchronization between a processor and a device by changing the delay time.
26. The system of claim 25 , wherein the time between receiving the test signal and sending the response signal is dependent on operating characteristics of the device.
27. The system of claim 26 , wherein the operating characteristics of the device include a voltage.
28. The system of claim 26 , wherein the operating characteristics of the device include a current.
29. The system of claim 26 , wherein the operating characteristics of the device include temperature.
30. The system of claim 26 , wherein the operating characteristics of the device are installation or production dependent.