Control of a piezoelectric motor

1. A method for controlling a piezoelectric motor, wherein control signals of the motor are periodic non-sinusoidal voltage signals having a triangular or triangle-truncated shape, each control signal being obtained by applying to an inductive element, forming with equivalent capacitors of the motor a non-resonant LC filter, a periodic signal generated by a digital state machine, and each period of the digital periodic signal being formed of at least two different variable series of sub-signals of same number of bits, each bit being able to take a state selected from among first and second values and in a variable series, a sub-signal being able to take a value different from either one of or both its neighboring two sub-signals.

2. The method of claim 1 , wherein each period of a signal generated by the state machine comprises at least:

a first series of sub-signals in which a selected quantity of most significant bits of the first value of the sub-signal becomes of the second value;

a given integral number of repetitions of a first single-bit signal formed of the bit of the second value;

a second series of sub-signals, inverse to the first series, in which a same selected quantity of least significant bits having the second value of the preceding sub-signal becomes of the first value; and

the given number of repetitions of a single-bit signal formed of the bit of the first value.

3. The method of claim 2 , wherein the sub-signal sampling frequency is 2 MHz, the number of bits being ten, and wherein:

the selected quantity is equal to one;

the number of repetitions ranges between 0 and 25;

the first sub-signal of the first series only comprises bits of the first value;

the last sub-signal of the first series only comprises bits of the second value;

the first sub-signal of the second series only comprises bit of the second value; and

the last sub-signal of the second series only comprises bits of the first value.

4. The method of claim 2 , wherein the sub-signal sampling frequency is 2 MHz, the number of bits being ten, and wherein:

the selected quantity is greater than one;

the first sub-signal of the first series comprises at least one most significant bit of the second value;

the last sub-signal of the first series comprises at least one least significant bit of the first value and is repeated to reach the minimum half-period corresponding to a desired maximum frequency value;

the first sub-signal of the second series comprises at least one least significant bit of the first value; and

the last sub-signal of the second series comprises at least one most significant bit of the second value and is repeated to reach the end of a minimum period corresponding to a desired maximum frequency value.

5. A piezoelectric motor, associated with a control circuit capable of implementing the method of claim 1 to provide two phase-shifted motor control voltage signals.

6. A photographic lens, comprising means capable of cooperating with the motor of claim 5 .

7. A photographic device, comprising the lens of claim 6 .

8. A telephone device, comprising the photographic device of claim 7 .

9. A method of controlling a piezoelectric motor, the method comprising:

generating a digital signal comprising a series of bits;

filtering the digital signal to produce a control signal having a triangular or triangle-truncated shape; and

controlling the piezoelectric motor using the control signal;

wherein generating the digital signal comprises generating a periodic series of bits, each period comprising a plurality of sub-signals of a same number of bits, each bit having a first value or a second value, wherein generating the plurality of sub-signals comprises:

generating a first series of sub-signals in which a quantity of bits of the first value increases for later sub-signals of the first series of sub-signals, wherein the first series of sub-signals, when filtered, produces an increasing portion of the control signal; and

generating a second series of sub-signals in which a quantity of bits of the first value decreases for later sub-signals of the second series of sub-signals, wherein the second series of sub-signals, when filtered, produces a decreasing portion of the control signal.

10. The method of claim 9 , wherein filtering the digital signal comprises filtering with a non-resonant LC filter.

11. The method of claim 10 , wherein filtering the digital signal comprises passing the digital signal through an inductor having an inductance value of less than or equal to 3 μH.

12. The method of claim 9 , wherein:

one or more most significant bits of each sub-signal of the first series of sub-signals has the first value; and

one or more least significant bits of each sub-signal of the second series of sub-signals has the first value.

13. A control circuit for controlling a piezoelectric motor using a control signal, the circuit comprising:

a digital circuit that generates a digital signal comprising a series of bits; and

an inductor that filters the digital signal to produce a control signal having a triangle or triangle-truncated shape;

wherein the digital signal generator generates the digital signal which comprises a periodic series of bits, each period comprising a plurality of sub-signals of a same number of bits, each of the bits having a first value or a second value, the plurality of sub-signals comprising:

a first series of sub-signals in which a quantity of bits of the first value increases for later sub-signals of the first series of sub-signals; and

a second series of sub-signals in which a quantity of bits of the first value decreases for later sub-signals of the second series of sub-signals.

14. The control circuit of claim 13 , wherein the digital circuit comprises a digital state machine.

15. The control circuit of claim 13 , wherein the inductor has an inductance value of less than or equal to 3 μH.

16. The control circuit of claim 13 , wherein:

the first series of sub-signals, when filtered, provide an increasing portion of the control signal;

wherein the second series of sub-signals, when filtered, provide a decreasing portion of the control signal.

17. The control circuit of claim 13 , wherein:

one or more most significant bits of each sub-signal of the first series of sub-signals has the first value; and

one or more least significant bits of each sub-signal of the second series of sub-signals has the first value.