A data processor having: an instruction fetch unit for acquiring an instruction; and an instruction execution unit for execution, by pipeline processing, the instruction acquired by the instruction fetch unit. In the data processor, the instruction execution unit includes an execution pipeline pipelined into two or more stages for execution of the execution instruction, and an execution pipeline control unit capable of changing a stage to arrange an operation by the execution unit in according to the number of wait cycles until data required for execution of the execution instruction is fixed. The stage, where an operation by the execution unit is arranged, is changed according to the number of wait cycles until the data is fixed, whereby the number of input-fixing wait cycles increased by pipelining cache access can be reduced.
1. A data processor comprising:
an instruction fetch unit for acquiring an instruction; and
an instruction execution unit for execution, by pipeline processing, the instruction acquired by the instruction fetch unit,
wherein the instruction execution unit includes
an execution unit for realizing an execution function of an execution instruction,
an execution pipeline pipelined into two or more stages for execution of the execution instruction, and
an execution pipeline control unit capable of changing a stage to arrange an operation by the execution unit according to a number of wait cycles until data required for execution of the execution instruction in the execution pipeline is fixed.
2. A data processor comprising:
an instruction fetch unit for acquiring an instruction; and
an instruction execution unit for execution, by pipeline processing, the instruction acquired by the instruction fetch unit,
wherein the instruction includes a load instruction for directing load of data, and
the instruction execution unit includes
an execution unit for realizing an execution function of an execution instruction,
an execution pipeline pipelined into two or more stages for execution of the execution instruction, and
an execution pipeline control unit capable of changing a point where data loaded by execution of the load instruction is used in an operation by the execution unit according to a number of wait cycles until the data is fixed in the execution pipeline.
3. The data processor of claim 1 , wherein the execution pipeline control unit accepts a result of access to a data cache as data required for execution of the execution instruction in the execution pipeline.
4. The data processor of claim 3 , wherein the execution pipeline control unit arranges an operation by the execution unit in a stage such that the number of wait cycles until the data is fixed is minimum.
5. The data processor of claim 3 , wherein when an attempt to arrange an operation by the execution unit in a stage used in execution of another execution instruction is made, the execution pipeline control unit arranges the operation by the execution unit in a stage further behind the stage in use.
6. The data processor of claim 3 , wherein a number of cycles required for execution of the execution instruction using the result of access to a data cache can be varied depending on an instruction executed prior to the execution instruction.
7. The data processor of claim 3 , wherein the execution pipeline includes
two or more inter-stage registers, each capable of holding a result of an execution in the execution unit, and
a selector capable of making a selection from among outputs of the two or more inter-stage registers,
wherein the selection from among the outputs of the inter-stage registers by the selector enables change of a stage where an operation by the execution unit is arranged.
8. The data processor of claim 3 , wherein the execution pipeline control unit includes:
a first pipeline capable of holding a signal showing validity of register writing and information on a stage where an operation by the execution unit is arranged;
a second pipeline capable of holding a register number of a register written into the register according to the instruction;
a third pipeline capable of holding a register number of a register read out from the register according to the instruction; and
a read register number generation circuit for selectively supplying an output of the third pipeline to the execution pipeline based on an putout of the first pipeline.