IP Library Granted Patent US 8,852,851
Granted Patent B2
US 8,852,851 · App. 11/484,271 · Granted Oct 7, 2014

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

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Quick Facts
Patent No.
US 8,852,851
App. No.
11/484,271
Granted
Oct 7, 2014
Kind
B2
Abstract

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Claims (17)

1. A method used during fabrication of a semiconductor device, the method comprising:

providing a layer to be etched, the layer to be etched having a substantially planar elevationally outermost surface;

forming a plurality of sacrificial first spacers on the outermost surface;

forming a second spacer layer over the plurality of sacrificial first spacers;

removing a portion of the second spacer layer to form a plurality of triads of spacers on the outermost surface, the triads comprising the first spacer bracketed by second spacers on the surface with each of the spacers within the triad having a different elevational thickness and the second spacers contacting the first spacer;

forming a conformal layer over the triad;

removing a portion of the conformal layer to form groups of five adjacent spacers, the individual groups comprising the triad bracketed by third spacers; removing the second spacers; and

etching the layer to be etched using the first and third spacers as a pattern to form a plurality of substantially similar features within the layer to be etched.

2. The method of claim 1 wherein the etching forms recesses aligned substantially equidistant along the outermost surface of the layer to be etched.

3. The method of claim 1 wherein the surfaces of all of the spacers are non-planar.

4. The method of claim 1 wherein the forming the second spacer layer on the plurality of sacrificial first spacers comprises providing a spacing layer to fill between some of the first spacers but not filling between all of the first spacers.

5. The method of claim 4 wherein the spacing layer alternates between filled and unfilled between first spacers in one cross section of the device.

6. The method of claim 1 wherein each spacer within the group of five spacers has a different elevational thickness.

7. The method of claim 1 wherein the groups of five spacers are spaced apart from one another.

8. The method of claim 1 wherein individual spacers within the groups of five spacers contact one another.

9. The method of claim 1 wherein the groups of five spacers are spaced apart from one another a distance that is substantially the same as the width of the second spacers.

10. The method of claim 1 wherein upon removal of the second spacers, the remaining spacers are substantially equally spaced along the surface to be etched.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 064857/0127 →
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2014
From: ZHOU, BAOSUO; ABATCHEV, MIRZAFER K.; NIROOMAND, ARDAVAN; MORGAN, PAUL A.; MENG, SHUANG; GREELEY, JOSEPH N.; COPPA, BRIAN J.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 033672/0231 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2006
From: ZHOU, BAOSUO; ABATCHEV, MIRAZFER K.; NIROOMAND, ARDAVAN; MORGAN, PAUL A.; MENG, SHUANG; GREELEY, JOSEPH N.
To: MICRON TECHNOLOGY INC.
Reel/Frame 018282/0155 →