Dual channel heterostructure
View Patent ↗Dual channel heterostructures comprising strained Si and strained Ge-containing layers are disclosed, along with methods for producing such structures. In preferred embodiments, a strain-relaxed buffer layer is deposited on a carrier substrate, a strained Si layer is deposited over the strain-relaxed buffer layer and a strained Ge-containing layer is deposited over the strained Si layer. The structure can be transferred to a host substrate to produce the strained Si layer over the strained Ge-containing layer. By depositing the Si layer first, the process avoids Ge agglomeration problems.
1. A method for producing a dual-channel heterostructure, the method comprising:
depositing a Si 1-x Ge x buffer layer, where x is a number between 0 and 1, on a carrier substrate comprising a single-crystal silicon structure;
depositing a strained silicon layer over the Si 1-x Ge x buffer layer;
depositing a compressively strained germanium-containing layer over the strained silicon layer;
providing a host substrate over the compressively strained germanium-containing layer; and
removing the carrier substrate and the Si 1-x Ge x buffer layer.
2. The method of claim 1 , wherein the carrier substrate is a bulk silicon substrate.
3. The method of claim 1 , wherein the Si 1-x Ge x buffer layer is strain-relaxed.
4. The method of claim 1 , wherein the single crystal silicon structure comprises an epitaxial silicon layer deposited on the carrier substrate.
5. The method of claim 1 , further comprising forming an epitaxial germanium layer on the carrier substrate prior to depositing the Si 1-x Ge x buffer layer.
6. The method of claim 5 , wherein the Si 1-x Ge x buffer layer is graded such that the concentration of germanium decreases from an interface with the epitaxial germanium layer to an interface with the strained silicon layer.
7. The method of claim 1 , wherein the strained silicon layer is tensile strained.
8. The method of claim 1 , wherein removing comprises chemical mechanical polishing (CMP).
9. The method of claim 1 , further comprising forming an etch-stop barrier layer on the Si 1-x Ge x buffer layer.
10. The method of claim 1 , wherein the Si 1-x Ge x buffer layer comprises Si 0.5 Ge 0.5 .
11. The method of claim 10 , wherein Si 0.5 Ge 0.5 is deposited using SiH 3 GeH 3 as a precursor.
12. The method of claim 1 , wherein the Si 1-x Ge x buffer layer is graded.
13. The method of claim 1 , wherein a surface of the host substrate comprises an insulator.
14. The method of claim 13 , wherein the surface of the host substrate is disposed between the host substrate and the compressively strained germanium-containing layer.
15. The method of claim 13 , wherein the insulator is SiO 2 .
16. The method of claim 1 , wherein at least one of the Si 1-x Ge x buffer layer, the strained silicon layer and the compressively strained germanium-containing layer is deposited by CVD.
17. The method of claim 1 , wherein the Si 1-x Ge x buffer layer, the strained silicon layer and the compressively strained germanium-containing layer are deposited in situ.
18. The method of claim 1 , additionally comprising forming one or more CMOS devices in the dual-channel heterostructure.
19. The method of claim 1 , wherein providing a host substrate comprises bonding the host substrate to the compressively strained germanium-containing layer.
20. The method of claim 1 , further comprising depositing a Si 1-x Ge x film, where x is a number between 0 and 1, over the compressively strained germanium-containing layer prior to providing the host substrate over the strained germanium-containing layer.
21. The method of claim 20 , wherein providing a host substrate comprises bonding the host substrate to the Si 1-x Ge x film.