Modular integrated circuit chip carrier
An apparatus and method is disclosed that allows for the arranging in a three dimensional array semiconductor chips on a circuit board. A unique chip carrier is disclosed on which any IC chip can be positioned on above the other on a circuit board. Additionally, the carrier allows for the testing of IC chips on the carrier and underneath it without having to remove the carrier and chips from the system even if they are of the BGA or CSP type. The carrier includes exposed test points to allow an on site test.
1. A carrier comprising:
a first platform comprising a non-ceramic printed circuit board having a top surface with ball grid array pads on said top surface for receiving at least one packaged integrated circuit chip, a bottom surface, a plurality of layers including a routing layer, and a plurality of conductive paths coupled with said ball grid array pads, at least one surface of at least one of said conductive paths being adjacent to said routing layer;
a second platform comprising a non-ceramic printed circuit board having a top surface with ball grid array pads on said top surface for receiving at least one packaged integrated circuit chip, and a bottom surface;
a first strut coupled to a first side of the bottom surface of said first platform and to an analogous first side of the top surface of said second platform, and comprising a plurality of strut vias that extend up through said first strut from the bottom of said first strut to the top of said first strut, wherein each strut via connects to a conductive path in said first platform; and
a second strut coupled to a second side of the bottom surface of said first platform and to an analogous second side of the top surface of said second platform, and comprising a plurality of strut vias that extend up through said second strut from the bottom of said second strut to the top of said second strut, wherein each strut via connects to a conductive path in said first platform.
2. The carrier of claim 1 further comprising a third strut, wherein said third strut is coupled to a third side of the bottom surface of said first platform and to an analogous third side of the top surface of said second platform.
3. The carrier of claim 2 wherein said third strut has strut vias that extend up from the bottom of said strut to the top of said strut wherein each of said strut vias connect to a conductive path in said first platform which conductive path connects to a via descending from a pad of the ball grid array pads.
4. The carrier of claim 2 further comprising a fourth strut, wherein said fourth strut is coupled to a fourth side of the bottom surface of said first platform and to an analogous fourth side of the top surface of said second platform.
5. The carrier of claim 4 wherein said fourth strut has strut vias that extend up from the bottom of said strut to the top of said strut wherein each of said strut vias connect to a conductive path in said platform which conductive path connects to a via descending from a pad of the ball grid array pads.
6. The carrier of claim 1 wherein said second platform further comprises a ball grid array on the bottom surface of said second platform.
7. A carrier comprising:
a) a first platform with a top surface, a bottom surface, and a plurality of layers including a routing layer wherein said routing layer is adjacent to a conductive path;
b) at least a first and a second strut; and
c) a second platform with a top surface and a bottom surface;
d) wherein said first strut is coupled to a first side of the bottom surface of said first platform and to a first side of the top surface of said second platform, and wherein said second strut is coupled to a second side of the bottom surface of said first platform and to a second side of the top surface of said second platform;
e) wherein said first platform has ball grid array pads on its top surface for receiving at least one packaged integrated circuit chip, a bottom side of each pad of said ball grid array being connected to a via that passes down through said first platform to a lower layer in said platform and connects to a conductive path that extends towards said first or second strut;
f) wherein said second platform has ball grid array pads on its top surface for receiving at least one packaged integrated circuit chip;
g) wherein said first and second struts have strut vias that extend up through each strut from the bottom of said strut to top of said strut and connect to conductive paths in said first platform; and
h) wherein said carrier forms a modular unit that can accept at least one packaged integrated circuit chip on said ball grid array pads on the top surface of said first platform and can accept a second integrated circuit chip on said ball grid array pads on the top surface of said second platform.
8. The carrier of claim 7 wherein said second platform further comprises a ball grid array on the bottom surface of said second platform.
9. The carrier of claim 7 further comprising a third and fourth strut.
10. A carrier comprising:
a platform comprising a non-ceramic printed circuit board having:
a top surface with ball grid array pads;
a bottom surface;
a plurality of layers including a routing layer wherein said routing layer is adjacent to a conductive path;
a plurality of platform vias conductively coupled to said ball grid array pads;
a first strut coupled to a first side of the bottom surface of said platform and comprising a plurality of strut vias and ball grid array, wherein each ball of said ball grid array is conductively coupled to a strut via; and
a second strut coupled to a second side of the bottom surface of said platform and comprising a plurality of strut vias and a ball grid array, wherein each ball of said ball grid array is conductively coupled to a strut via;
wherein each of said platform vias is conductively coupled to at least one strut via and each of said platform vias is conductively coupled to each other by said conductive path.
11. The carrier of claim 10 further comprising a packaged integrated circuit chip coupled to said ball grid array pads on said top surface of said platform.
12. The carrier of claim 10 wherein said carrier is coupled to a printed circuit board.
13. The carrier of claim 12 wherein an integrated circuit chip is coupled to said printed circuit board beneath said platform.
14. The carrier of claim 10 wherein at least one of said plurality of strut vias and said plurality of platform vias are aligned.
15. The carrier of claim 10 wherein at least one of said plurality of strut vias and said plurality of platform vias are staggered.
16. An electronic circuit module comprising:
a printed circuit board;
a platform comprising:
a top surface with a ball grid array pads;
a bottom surface; and
a plurality of layers including a routing layer wherein said routing laver is adjacent to a conductive path;
a plurality of platform vias conductively coupled with said ball grid array pads;
a first strut coupled to a first side of the bottom surface of said platform and comprising a plurality of strut vias and a ball grid array coupled to said printed circuit board, wherein each ball of said ball grid array is conductively coupled to a strut via; and
a second strut coupled to a second side of the bottom surface of said platform and comprising a plurality of strut vias and a ball grid array coupled to said printed circuit board, wherein each ball of said ball grid array is conductively coupled to a strut via,
wherein each of said platform vias is conductively coupled to at least one strut via and each of said platform vias is conductively coupled to each other by said conductive path.
17. The electronic module of claim 16 further comprising a first packaged integrated circuit chip coupled to the top surface of said platform.
18. The electronic module of claim 17 further comprising a second packaged integrated circuit chip coupled to said printed circuit board and beneath said platform.