Method for controlling nonvolatile memory device
View Patent ↗Data is written to a nonvolatile memory device having a memory region of four bits or larger in one memory cell sandwiched by a source and a drain with an improved accuracy. The nonvolatile memory device 100 includes four control gates 114 to 117 provided between a first and a second impurity-diffused regions 106 a and 160 b that are provided separately from the semiconductor substrate, and a memory cell including memory regions 106 a to 106 d that are counterpart of the control gates. A method for controlling the nonvolatile memory device 100 includes classifying the four control gates 114 to 100 into two groups of right and left sides, and then, applying a lower voltage to an impurity-diffused region that is further from a target memory region for injecting an electron and applying a higher voltage to an impurity-diffused region that is closer the target memory region, and moreover applying a higher voltage, the higher voltage being higher than voltages applied to other control gates.
1. A method for controlling a nonvolatile memory device, said nonvolatile memory device comprising:
a semiconductor substrate; and
a memory cell including:
first and second impurity-diffused regions provided separately and spaced from each other at the surface of said semiconductor substrate;
first to Nth control gates, where N is an even number of not smaller than four, being disposed in parallel with each other between said first impurity-diffused region and said second impurity-diffused region in this order on said semiconductor substrate; and
first to Nth memory regions, respectively being provided between said semiconductor substrate and said first to said Nth control gates,
said method comprising:
(a) classifying said first to Nth control gates into a first control gate group composed of first to N/2th control gates arranged in a side of said first impurity-diffused region and a second control gate group composed of (N/2+1)th to Nth control gates arranged in a side of said second impurity-diffused region, and then applying a first higher voltage to said first impurity-diffused region and applying a first lower voltage to said second impurity-diffused region when a target control gate corresponding to a target memory region for injecting an electron is included in said first control gate group, and applying a second lower voltage to said first impurity-diffused region and applying a second higher voltage to said second impurity-diffused region when said target control gate is included in said second control gate group; and
(b) applying a third higher voltage to said target control gate, while the condition of applying said voltages to said first and said second impurity-diffused regions is maintained, so that electron is injected to said target memory region that is corresponding to said target control gate, said third higher voltage being higher than voltages applied to other control gates.
2. The method for controlling the nonvolatile memory device according to claim 1 , wherein in said (b), if a control gate other than said target control gate is disposed between said impurity-diffused region that is applied with said first or second higher voltage and said target control gate, applying a fourth higher voltage to said control gate disposed between said impurity-diffused region that is applied with said first or second higher voltage and said target control gate, said fourth higher voltage being higher than voltages applied to said control gates disposed between said impurity-diffused region that is applied with said first or second lower voltage and said target control gate.
3. The method for controlling the nonvolatile memory device according to claim 1 , wherein said first control gate is provided to be adjacent to said first impurity-diffused region, and wherein in said (b), when said first impurity-diffused region is applied with said second lower voltage, a third lower voltage is applied to said first control gate, said third lower voltage being lower than a voltage applied to other control gates included in said first control gate group.
4. The method for controlling the nonvolatile memory device according to claim 2 , wherein said first control gate is provided to be adjacent to said first impurity-diffused region, and wherein in said (b), when said first impurity-diffused region is applied with said second lower voltage, a third lower voltage is applied to said first control gate, said third lower voltage being lower than a voltage applied to other control gates included in said first control gate group.
5. The method for controlling the nonvolatile memory device according to claim 1 , wherein said Nth control gate is provided to be adjacent to said second impurity-diffused region, and wherein in said (b), when said second impurity-diffused region is applied with said first lower voltage, a fourth lower voltage is applied to said Nth control gate, said fourth lower voltage being lower than a voltage applied to other control gates included in said second control gate group.
6. The method for controlling the nonvolatile memory device according to claim 2 , wherein said Nth control gate is provided to be adjacent to said second impurity-diffused region, and wherein in said (b), when said second impurity-diffused region is applied with said first lower voltage, a fourth lower voltage is applied to said Nth control gate, said fourth lower voltage being lower than a voltage applied to other control gates included in said second control gate group.
7. The method for controlling the nonvolatile memory device according to claim 1 , wherein said first to said Nth control gates in said nonvolatile memory device are arranged to be adjacent in this order such that only an insulating film is disposed between the adjacent control gates.
8. The method for controlling the nonvolatile memory device according to claim 2 , wherein said first to said Nth control gates in said nonvolatile memory device are arranged to be adjacent in this order such that only an insulating film is disposed between the adjacent control gates.
9. The method for controlling the nonvolatile memory device according to claim 1 , wherein said first to said Nth control gates in said nonvolatile memory device are symmetrically arranged in a cross-section in a gate length direction.
10. The method for controlling the nonvolatile memory device according to claim 2 , wherein said first to said Nth control gates in said nonvolatile memory device are symmetrically arranged in a cross-section in a gate length direction.
11. The method for controlling the nonvolatile memory device according to claim 7 , wherein said first to said Nth control gates in said nonvolatile memory device are symmetrically arranged in a cross-section in a gate length direction.
12. The method for controlling the nonvolatile memory device according to claim 1 , further comprising:
(c) determining a sequence for injecting electron to said first to said Nth memory regions, when injecting electron to said first to said Nth memory regions is required, corresponding to data code for being stored in said memory cell; and
(d) sequentially selecting said target memory region for being injected with electron from said first to said Nth memory regions, according to the sequence determined in said determining the sequence for injecting electron,
wherein said (a) and said (b) are conducted over the control gate corresponding to said target memory region selected in said (d).
13. The method for controlling the nonvolatile memory device according to claim 12 , further comprising:
(e) determining electrical voltages being applied to said first to said Nth control gates in said (b) before injecting electron into said target memory region selected in said (d), in view of a fact whether electron is injected into any other of said memory regions in the same memory cell or not, according to said injection sequence determined in said (c),
wherein, in said (b), electrical voltages determined in said (e) are applied to said first to said Nth control gates.