CMOS image sensor and manufacturing method thereof
View Patent ↗Disclosed are a CMOS image sensor and a manufacturing method thereof. The method includes the steps of: forming an isolation layer on a semiconductor substrate, defining an active region that includes a photo diode region and a transistor region; forming a gate in the transistor region, the gate including a gate electrode and a gate insulating layer; forming a first low-concentration diffusion region in the photo diode region; forming a second low-concentration diffusion region in the transistor region; forming a buffer layer over the substrate, the buffer layer covering the photo diode region; forming first and second insulating layers over the entire surface of the substrate, the first and second insulating layer having a different etching selectivity from each other; forming an insulating sidewall on sides of the gate electrode by selective removal of the second insulating layer; removing the first insulating layer from the transistor region; forming a high-concentration diffusion region in the exposed transistor region, partially overlapping the second low-concentration diffusion region; and forming a metal silicide layer on the high-concentration diffusion region.
1. A method for manufacturing a CMOS image sensor, comprising the steps of:
forming an isolation layer on a semiconductor substrate, the isolation layer defining an active region including a photo diode region and a transistor region;
forming a gate in the transistor region, the gate including a gate insulating layer and a gate electrode thereon;
forming a first low-concentration diffusion region in the photo diode region;
forming a second low-concentration diffusion region in the transistor region;
forming a buffer layer over the substrate, the buffer layer having an opening exposing the transistor region;
forming first and second insulating layers over an entire surface of the substrate, including on the buffer layer in the photo diode region, the first and second insulating layers having a different etching selectivity from each other;
forming an insulating sidewall on sides of the gate electrode by selective removal of the second insulating layer, including on the first insulating layer in the transistor region and the photo diode region, and on the buffer layer in the photo diode region;
selectively removing the first insulating layer to expose the transistor region;
forming a high-concentration diffusion region in the exposed transistor region, partially overlapping the second low-concentration diffusion region; and
forming a metal silicide layer on a surface of the high-concentration diffusion region.
2. The method of claim 1 , wherein the first insulating layer comprises an oxide.
3. The method of claim 1 , wherein the second insulating layer comprises a nitride.
4. The method of claim 2 , wherein the first insulating layer comprises a thermal oxide layer or a TEOS-based oxide layer.
5. The method of claim 1 , wherein the buffer layer comprises O 3 -TEOS or BPSG.
6. The method of claim 1 , wherein selectively removing the buffer layer comprises etching with an etchant comprising a silane gas.
7. The method of claim 1 , further comprising the step of heat-treating the substrate after forming the first and second low-concentration diffusion regions.
8. The method of claim 7 , further comprising the step of heat-treating the substrate after forming the high-concentration diffusion region.
9. The method of claim 8 , wherein the first and second heat-treatments are performed at a temperature of 800° C.˜1200° C.
10. The method of claim 1 , further comprising the steps of:
forming a diffusion and/or etching blocker over the entire surface of the substrate, after forming the metal silicide layer; and
selectively removing the diffusion and/or etching blocker over the photo diode region.
11. The method of claim 10 , further comprising the step of forming a dielectric layer over the entire surface of the substrate including the remaining diffusion and/or etching blocker.
12. The method of claim 10 , wherein the diffusion and/or etching blocker comprises a nitride layer.
13. The method of claim 11 , wherein the dielectric layer comprises a silane-based insulating material.
14. The method of claim 1 , wherein the buffer layer has a thickness of 400 Ř3000 Å.