Semiconductor integrated circuit device
View Patent ↗In a semiconductor integrated circuit device, a VDD wiring trace and a GND wiring trace are routed along an N-well and a P-well, respectively, within a substrate. A substrate-bias VDD2 wiring trace is routed in a direction that intersects the VDD wiring trace and GND wiring trace in the same layer thereof and is electrically connected thereto. A P+ diffusion layer is disposed in the N-well in the vicinity of a portion where the wiring directions of the VDD wiring trace and substrate-bias VDD2 wiring trace intersect and is electrically connected to the VDD wiring trace via a contact. An N+ diffusion layer is disposed in the P-well in the vicinity of a portion where the wiring directions of the GND wiring trace and substrate-bias VDD2 wiring trace intersect and is electrically connected to the GND wiring trace via a contact. The P+ diffusion layer is used as a wiring route regarding the VDD wiring trace and the N+ diffusion layer is used as a wiring route regarding the GND wiring trace.
1. A semiconductor integrated circuit device comprising:
a first wiring trace routed along a well of a first conductivity type in a substrate;
a second wiring trace routed along a well of a second conductivity type in the substrate;
a third wiring trace disposed in the same layer as said first and second wiring traces, routed in a direction that intersects said first and second wiring traces and electrically insulated from said first and second wiring traces;
a first diffusion layer of the second conductivity type disposed in the well of the first conductivity type in the vicinity of a portion where the wiring directions of said first and third wiring traces intersect, and electrically connected to said first wiring trace through a contact; and
a second diffusion layer of the first conductivity type disposed in the well of the second conductivity type in the vicinity of a portion where the wiring directions of said second and third wiring traces intersect, and electrically connected to said second wiring trace through a contact;
wherein said first diffusion layer is used as a wiring route regarding said first wiring trace, and said second diffusion layer is used as a wiring route regarding said second wiring trace.
2. The device according to claim 1 , further comprising a fourth wiring trace disposed in the same layer as that of said first and second wiring traces, routed in a direction that intersects said first and second wiring traces, electrically insulated from said first and second wiring traces and spaced a prescribed distance away from said third wiring trace;
wherein in the vicinity of a portion where the wiring directions of said first and fourth wiring traces intersect, said first diffusion layer is electrically connected to said first wiring trace through a contact and is used as a wiring route regarding said first wiring trace; and
in the vicinity of a portion where the wiring directions of said second and fourth wiring traces intersect, said second diffusion layer is electrically connected to said second wiring trace through a contact and is used as a wiring route regarding said second wiring trace.
3. The device according to claim 2 , wherein said first and second wiring traces are formed in a wiring layer closest to the side of the substrate among wiring layers formed on said substrate.
4. The device according to claim 1 , wherein said first and second wiring traces are formed in a wiring layer closest to the side of the substrate among wiring layers formed on said substrate.
5. A semiconductor integrated circuit device that includes cell placement areas in which a plurality of standard cells are placed on a semiconductor substrate, said device comprising:
a first power-supply line for supplying a first power-supply potential to the standard cells;
a second power-supply line, which is routed parallel to said first power-supply line, for supplying a second power-supply potential to the standard cells;
a third power-supply line, which is routed in a direction that intersects said first power-supply line, for supplying a third power-supply potential to a well of a first conductivity type in the cell placement areas;
a fourth power-supply line, which is routed parallel to said third power-supply line, for supplying a fourth power-supply potential to a well of a second conductivity type in the cell placement areas;
first and second substrate-bias supply cells disposed in the cell placement areas;
a first diffusion layer of the second conductivity type disposed in the well of the first conductivity type and electrically connected to said first power-supply line through a contact; and
a second diffusion layer of the first conductivity type disposed in the well of the second conductivity type and electrically connected to said second power-supply line through a contact;
wherein said first, second, third and fourth power-supply lines are formed in a first metal wiring layer of said semiconductor integrated circuit device;
said first substrate-bias supply cell includes:
said third power-supply line;
a first well contact connected to said third power-supply line for supplying the third power-supply potential to the well of the first conductivity type;
said first diffusion layer; and
said second diffusion layer;
said second substrate-bias supply cell includes:
said fourth power-supply line;
a second well contact connected to said fourth power-supply line for supplying the fourth power-supply potential to the well of the second conductivity type;
said first diffusion layer; and
said second diffusion layer; and
in said first and second substrate bias supply cells, said first diffusion layer is used as a wiring route regarding said first power-supply line and said second diffusion layer is used as a wiring route regarding said second power-supply line.
6. The device according to claim 5 , wherein the first metal wiring layer is a wiring layer formed in a wiring layer closest to the side of the substrate among wiring layers formed on said substrate.
7. The device according to claim 6 , wherein in said first and second substrate-bias supply cells, said first and second power-supply lines are routed so as to detour around the second metal wiring layer.
8. The device according to claim 7 , wherein said first substrate-bias supply cell has a first MOS transistor in which parts of said second diffusion layer are formed as a source and drain.
9. The device according to claim 8 , wherein a gate electrode of said first MOS transistor is connected to said third power-supply line through a via or is floating.
10. The device according to claim 7 , wherein said second substrate-bias supply cell has a second MOS transistor in which parts of said first diffusion layer are formed as a source and drain.
11. The device according to claim 5 , wherein said first substrate-bias supply cell has a first MOS transistor in which parts of said second diffusion layer are formed as a source and drain.
12. The device according to claim 11 , wherein a gate electrode of said first MOS transistor is connected to said third power-supply line through a via or is floating.
13. The device according to claim 11 , wherein said second substrate-bias supply cell has a second MOS transistor in which parts of said first diffusion layer are formed as a source and drain.
14. The device according to claim 5 , wherein said second substrate-bias supply cell has a second MOS transistor in which parts of said first diffusion layer are formed as a source and drain.
15. The device according to claim 14 , wherein a gate electrode of said second MOS transistor is connected to said fourth power-supply line through a via or is floating.
16. The device according to claim 14 , wherein said first and second MOS transistors function as capacitance elements provided between a short-circuited source and drain and a gate electrode.
17. The device according to claim 5 , wherein said first and second substrate-bias supply cells are arranged side by side as a pair.