IP Library Granted Patent US 7,488,627
Granted Patent B1
US 7,488,627 · App. 11/487,548 · Granted Feb 10, 2009

Thyristor-based memory and its method of operation

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Quick Facts
Patent No.
US 7,488,627
App. No.
11/487,548
Granted
Feb 10, 2009
Kind
B1
Abstract

A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.

Claims (15)

1. A method comprising:

operating a capacitively-coupled thyristor memory;

sensing a temperature of the capacitively-coupled thyristor memory; and

controlling a gain of a constituent bipolar transistor of a thyristor of the capacitively-coupled thyristor memory based on the temperature sensed.

2. A method comprising:

operating a capacitively-coupled thyristor memory;

sensing a temperature; and

controlling a gain of a bipolar transistor of a thyristor of the capacitively-coupled thyristor memory based on the temperature sensed;

in which the controlling the gain comprises affecting a voltage level of an electrode capacitively disposed over in insulated-adjacent relationship to a base region of the thyristor dependent on the temperature sensed.

3. A method comprising:

operating a capacitively-coupled thyristor memory;

sensing a temperature; and

controlling a gain of a bipolar transistor of a thyristor of the capacitively-coupled thyristor memory based on the temperature sensed;

the controlling the gain comprises affecting a voltage level of a supporting substrate beneath the thyristor dependent on the temperature sensed.

4. The method of claim 3 , in which the thyristor is formed in a silicon layer of a silicon on insulator (SOI) structure on the supporting substrate, and the affecting the voltage level comprises biasing the supporting substrate to influence an electric field through the base region between the electrode and the supporting substrate.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2013
From: T-RAM SEMICONDUCTOR, INC.
To: T-RAM (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 031694/0018 →
PURCHASE OPTION AGREEMENT Recorded Jun 3, 2010
From: T-RAM SEMICONDUCTOR, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 024474/0979 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2006
From: NEMATI, FARID; YANG, KEVIN J.
To: T-RAM
Reel/Frame 018066/0261 →