Method for machining a semiconductor wafer on both sides in a carrier, carrier, and a semiconductor wafer produced by the method
View Patent ↗A semiconductor wafer is guided in a cutout in a carrier while a thickness of the semiconductor wafer is reduced to a target thickness by material removal from the front and back surfaces simultaneously. The semiconductor wafer is machined until it is thinner than a carrier body and thicker than an inlay used to line the cutout in the carrier to protect the semiconductor wafer. The carrier is distinguished by the fact that the carrier body and the inlay have different thicknesses throughout the entire duration of the machining of the semiconductor wafer, the carrier body being thicker than the inlay, by from 20 to 70 μm. Themethod provides semiconductor wafers polished on both sides, having a front surface, a back surface and an edge, and a local flatness of the front surface, SFQR max of less than 50 nm with an edge exclusion of R-2 mm and less than nm with an edge exclusion of R-1 mm, based on a site area of 26 by 8 mm.
1. A method for machining a semiconductor wafer to a target thickness, comprising guiding the semiconductor wafer in a cutout of a carrier and reducing a thickness of the semiconductor wafer to a target thickness by removing material from a front surface and a back surface of the semiconductor wafer simultaneously, and machining the semiconductor wafer until it is thinner than the carrier and thicker than an inlay which lines the cutout in the carrier to protect the semiconductor wafer and which is thinner than the carrier, wherein the difference between the thickness of the carrier and the thickness of the inlay is in the range of 20 to 70 μm, and wherein the difference Δh between the target thickness of the semiconductor wafer and the thickness of the carrier body is −6 μm≦Δh<0 μm.
2. The method of claim 1 , wherein the semiconductor wafer is machined until material with a thickness of at least 5 μm has been removed.
3. The method of claim 2 , wherein the difference between the thickness of the carrier and the thickness of the inlay is between 30 μm and 60 μm.
4. The method of claim 1 , wherein the difference Δh between the target thickness of the semiconductor wafer and the thickness of the carrier body is −5 μm≦Δh≦−1 μm.
5. The method of claim 4 , wherein the semiconductor wafer is machined together with other semiconductor wafers using a set of carriers in which a mean thickness of the carrier bodies varies by no more than 3 μm.
6. The method of claim 1 , wherein the semiconductor wafer is machined together with other semiconductor wafers using a set of carriers in which a mean thickness of the carrier bodies varies by no more than 3 μm.