IP Library Granted Patent US 7,341,922
Granted Patent B2
US 7,341,922 · App. 11/487,968 · Granted Mar 11, 2008

Dry etching method, fabrication method for semiconductor device, and dry etching apparatus

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Quick Facts
Patent No.
US 7,341,922
App. No.
11/487,968
Granted
Mar 11, 2008
Kind
B2
Abstract

When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.

Claims (18)

1. A method for fabricating a semiconductor device using a dry etching apparatus having a dual power source capable of independently controlling source power and bias power, the method comprising the steps of:

forming a mask pattern having an opening corresponding to a region to be formed with an isolation on a silicon substrate;

placing the silicon substrate formed with the mask pattern in the chamber;

introducing a process gas containing at least oxygen into the chamber in which the silicon substrate has been placed; and

forming a trench for isolation in the silicon substrate by generating a plasma of the process gas with application of the source power, drawing ions from the plasma into the silicon substrate with application of the bias power. and thereby performing etching with respect to the silicon substrate,

wherein the step of forming a trench for isolation includes the step of applying the source power and the bias power such that an effective value of the source power reaches a second predetermined value after an effective value of the bias power reaches a first predetermined value, thereby initiating the application of the bias power before oxidization proceeds at an exposed portion of the silicon substrate.

2. The method of claim 1 , wherein the step of forming the trench for isolation, a time until the effective value of the bias power reaches the first predetermined value is shorter than a time until the effective value of the source power reaches the second predetermined value.

3. The method of claim 1 , wherein the step of performing etching with respect to the silicon substrate, an etching speed of a silicon oxide film is one hundredth or less of an etching speed of silicon.

4. A method for fabricating a semiconductor device using a dry etching apparatus having a dual power source capable of independently controlling source power and bias power, the method comprising the steps of:

forming a conductive film containing at least silicon on a substrate;

forming a mask pattern covering a region to be formed with a gate electrode on the conductive film;

placing the substrate formed with the conductive film and with the mask pattern in the chamber,

introducing a process gas containing at least oxygen into the chamber in which the substrate has been placed; and

forming a gate electrode composed of the conductive film by generating a plasma of the process gas with application of the source power, drawing ions from the plasma into the conductive film with application of the bias power, and thereby performing etching with respect to the conductive film,

wherein the step of forming the gate electrode includes the step of applying the source power and the bias power such that an effective value of the source power reaches a second predetermined value after an effective value of the bias power reaches a first predetermined value, thereby initiating the application of the bias power before oxidization proceeds at an exposed portion of the conductive film.

5. The method of claim 4 , wherein the step of forming the gate electrode, a time until the effective value of the bias power reaches the first predetermined value is shorter than a time until the effective value of the source power reaches the second predetermined value.

6. The method of claim 4 , wherein the conductive film is a polysilicon film, an amorphous silicon film, or a suicide film.

7. The method of claim 4 , wherein the step of performing etching with respect to the conductive film, an etching speed of a silicon oxide film is one hundredth or less of an etching speed of silicon.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2020
From: PANNOVA SEMIC, LLC
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 053755/0859 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →
CHANGE OF NAME Recorded Sep 19, 2014
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 033777/0873 →