Semiconductor device and method of manufacturing the same
View Patent ↗The method of manufacturing a semiconductor device according to the present invention includes: forming an interconnect trench in an insulating film formed on a semiconductor substrate (S 100 ); forming a barrier metal layer on the whole surface of the insulating film (S 102 ); forming a copper layer on the whole surface of the barrier metal layer so that the copper layer is embedded in the interconnect trench (S 104 ); removing the copper layer outside the interconnect trench by polishing under a condition that the barrier metal layer is left on the surface of the insulating film (S 106 ); selectively forming a cap metal layer on the copper layer formed in the interconnect trench after the step of removing the copper layer by polishing (S 108 ); and flattening the cap metal layer by polishing (S 110 ).
1. A semiconductor device, including:
a semiconductor substrate;
an insulating film formed on said semiconductor substrate;
an interconnect which is formed in said insulating film, and includes a copper layer with a plurality of orientations; and
a cap metal layer formed on a surface of said copper layer, the cap metal layer having a final layer thickness of 5 to 25 nm,
wherein an RMS value of a surface roughness of said cap metal layer is 10 nm or less.
2. The semiconductor device according to claim 1 ,
wherein said cap metal layer has a flattened surface.
3. The semiconductor device according to claim 1 ,
wherein said interconnect further includes a barrier metal layer, and
said cap metal layer is formed with a material different from that of said barrier metal layer.
4. The semiconductor device according to claim 2 ,
wherein said interconnect further includes a barrier metal layer, and
said cap metal layer is formed with a material different from that of said barrier metal layer.
5. The semiconductor device according to claim 1 ,
wherein said cap metal layer is formed with an amorphous material.
6. The semiconductor device according to claim 2 ,
wherein said cap metal layer is formed with an amorphous material.
7. The semiconductor device according to claim 3 ,
wherein said cap metal layer is formed with an amorphous material.
8. The semiconductor device according to claim 1 ,
wherein an upper surface of said cap metal layer is formed to substantially be flat with that of said insulating film.
9. The semiconductor device according to claim 2 ,
wherein an upper surface of said cap metal layer is formed to substantially be flat with that of said insulating film.
10. The semiconductor device according to claim 3 ,
wherein an upper surface of said cap metal layer is formed to substantially be flat with that of said insulating film.
11. The semiconductor device according to claim 4 ,
wherein an upper surface of said cap metal layer is formed to substantially be flat with that of said insulating film.
12. The semiconductor device according to claim 5 ,
wherein an upper surface of said cap metal layer is formed to substantially be flat with that of said insulating film.
13. The semiconductor device according to claim 6 ,
wherein an upper surface of said cap metal layer is formed to substantially be flat with that of said insulating film.
14. The semiconductor device according to claim 7 ,
wherein an upper surface of said cap metal layer is formed to substantially be flat with that of said insulating film.
15. The semiconductor device according to claim 1 , wherein the RMS value of the surface roughness of said cap metal layer is 5 nm or less.
16. The semiconductor device according to claim 1 , wherein the RMS value of the surface roughness of said cap metal layer is 2 nm or less.
17. The semiconductor device according to claim 1 , wherein the RMS value of the surface roughness of said cap metal layer is 2-5 nm.
18. The semiconductor device according to claim 1 , wherein a via resistance R due to the cap metal layer is determined by R=ρ×t/S, where ρ is the resistance rate of the cap metal, t is the film thickness of the cap metal and S is a base area of the via.
19. The semiconductor device according to claim 17 , wherein t=R×S/ρ, Δt=ΔR×S/ρ, and ΔR=0.5Ω, S=Π(50 nm) 2 , ρ=50 μΩcm, and Δt=7.9 nm.
20. The semiconductor device according to claim 1 , wherein a variation of the layer thickness of the cap metal layer is 7.9 nm or less.