Dynamic matching of signal path and reference path for sensing
View Patent ↗A method for operating a non-volatile memory cell device, the method including providing an array of memory array cells connected to word lines and local bit lines, the local bit lines being connected to global bit lines via select transistors, the array being divided into isolated sectors, providing a sense amplifier operative to sense the memory array cells via a sensing path that includes at least one of the local bit lines, at least one of the select transistors, at least one accessed global bit line, and a YMUX, providing a reference cell located in a reference mini-array, the reference cell being connected to the YMUX and being connected to the sense amplifier via another sensing path, driving both the memory array cells and the reference cells with a common bit line (BL) driver connected to the memory array cells and the reference cells via the YMUX through accessed global bit lines, and matching the sensing path of the memory array cell and the sensing path of the reference cell to the sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier. The non-accessed global bit line may be dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.
1. A method for operating a non-volatile memory cell device including a memory cell array with memory cells and reference cells, said method comprising:
driving a memory cell and a reference cell with a common bit line (BL) driver connected to the memory cell and the reference cell via a multiplexer through accessed global bit lines; and matching a sensing path of the memory cell and the reference cell sensing path to a sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier.
2. The method according to claim 1 , wherein the non-accessed global bit line is dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.
3. The method according to claim 1 , further comprising matching a coupling signal between the drain and source sides of the memory array cell and the reference cell by using a neighboring, non-accessed global bit line as the reference global bit line.
4. The method according to claim 3 , wherein capacitances of the sensing path of the memory array cell and of the sensing path of the reference cell are fully matched.
5. The method according to claim 1 , wherein the sensing comprises source side sensing, wherein said sense amplifier senses the source sides of the memory array cells, the accessed global bit line serving as a global source bit line, and wherein said common bit line (BL) driver drives drain sides of the memory array cells and the reference cells through the accessed global bit lines serving as global drain bit lines.
6. The method according to claim 1 , wherein the memory array cells and the reference cell comprise dual bit cells, each having a right side bit and a left side bit.
7. A non-volatile memory cell device comprising: a memory cell array with memory cells and reference cells, and control logic adapted to drive a memory cell and a reference cell with a common bit line (BL) driver connected to the memory cell and the reference cell via a multiplexer through accessed global bit lines; and matching a sensing path of the memory cell and the reference cell sensing path to a sense amplifier by using a non-accessed global bit line in the sensing path between the reference cell and the sense amplifier.
8. The device according to claim 7 , wherein the non-accessed global bit line is dynamically chosen as the global bit line adjacent to the global bit line used for driving both the drains of the array and the reference cells.
9. The device according to claim 7 , further comprising matching a coupling signal between a drain and source of the memory array cell and the reference cell by using a neighboring, non-accessed global bit line as a reference global bit line.
10. The device according to claim 9 , wherein capacitances of the sensing path of the memory array cell and of the sensing path of the reference cell are fully matched.
11. The device according to claim 7 , wherein the sensing comprises source side sensing, wherein said sense amplifier senses the source sides of the memory array cells, the accessed global bit line serving as a global source bit line, and wherein said common bit line (BL) driver drives drain sides of the memory array cells and the reference cells through the accessed global bit lines serving as global drain bit lines.
12. The device according to claim 7 , wherein the memory array cells and the reference cell comprise dual bit cells, each having a right side bit and a left side bit.