IP Library › Granted Patent US 7,541,244
Granted Patent B2
US 7,541,244 · App. 11/491,704 · Granted Jun 2, 2009

Semiconductor device having a trench gate and method of fabricating the same

Assignee: Nanya Technology Corporation
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Quick Facts
Patent No.
US 7,541,244
App. No.
11/491,704
Granted
Jun 2, 2009
Kind
B2
Abstract

A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.

Claims (15)

1. A method of fabricating a semiconductor device having a trench gate, comprising:

providing a semiconductor substrate having a trench etch mask thereon;

forming a first trench in the semiconductor substrate using the trench etch mask as a shield;

doping impurities into the semiconductor substrate along the first trench to form a doped region;

deepening the first trench to define a second trench in the semiconductor substrate so as to the semiconductor substrate of a bottom of the second trench free of the doped region;

forming a single gate insulating layer on a sidewall and a bottom of the second trench simultaneously, wherein a first portion of the single gate insulating layer on the sidewall of the second trench is thicker than a second portion of the single gate insulating layer on the bottom of the second trench; and

forming a trench gate in the second trench.

2. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1 , wherein the first depth of the first trench and the second depth of the second trench have a depth difference of about 300 Å to 500 Å.

3. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1 , wherein the doped region has a depth of about 100 Å to 500 Å.

4. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1 , wherein the gate insulating layer is formed by thermal oxidation.

5. The method of fabricating a semiconductor device having a trench gate as claimed in claim 1 , further comprising implanting ions into the doped region to form a source/drain region after forming the trench gate.

6. A method of fabricating a semiconductor device comprising:

forming a trench in a semiconductor substrate;

forming a doped region surrounding a sidewall of the trench and free of a bottom of the trench; and

forming a single insulating layer on the sidewall and the bottom of the trench simultaneously, wherein a thickness of the single insulating layer on the sidewall of the trench is thicker than the single insulating layer on the bottom of the trench.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2006
From: LIN, JENG-PING; LEE, PEI-ING
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 018054/0153 →
Priority Claims (1)
TW 94145039 A · Dec 19, 2005 · national
Continuity (1)
Related Publication 20070138545A1 · Jun 21, 2007