Impedance adjusting circuit and impedance adjusting method
View Patent ↗An impedance adjusting circuit for adjusting an impedance of an output buffer of a DDR2 memory, using an OCD impedance adjusting function, from a side of a memory controller, includes first and second terminals, first and second switches, a comparator, and a control circuit. The DDR2 memory has an OCD impedance adjusting function and includes a first output buffer and a second buffer each having a pull-up buffer and a pull-down buffer that receive an input signal in common and with impedances thereof capable of being variably set. The first and second terminals receive first and second signals output from the first buffer and the second buffers, respectively. The first and second switches are connected between the first terminal and the second terminal in series. The comparator compares a reference voltage VREF with a voltage at a connection node between the first and second switches. The control circuit receives a comparison result from the comparator to perform control for adjustably setting the impedance of the first buffer and/or the impedance of the second buffer, and also performs on/off control of the first and second switches.
1. An impedance adjusting circuit for adjusting an impedance of a semiconductor device including first and second output buffers with respective impedances thereof variably controlled, said impedance adjusting circuit comprising:
first and second terminals connected to outputs of said first and second output buffers, respectively;
first and second switches connected in series between said first and second terminals;
a comparator for comparing an input reference voltage with a voltage at a connection node between said first switch and said second switch; and
a control circuit for on/off controlling said first and second switches and receiving a comparison result from said comparator to perform control for adjustably setting the impedance of said first buffer and/or the impedance of said second buffer.
2. The impedance adjusting circuit according to claim 1 , wherein said control circuit turns on said first and second switches at a time of the impedance adjustment.
3. The impedance adjusting circuit according to claim 1 , wherein the first and second signals are output respectively from said first and second output buffers in opposite phases to each other.
4. The impedance adjusting circuit according to claim 1 , wherein said semiconductor device includes an OCD (Off-Chip Driver) impedance adjusting function, and wherein the impedances of said first and second output buffers are measured and adjusted using an OCD impedance adjusting mode.
5. The impedance adjusting circuit according to claim 4 , wherein said semiconductor device comprises a memory, the first and second signals from said first and second output buffers of said memory being connected to said first and second terminals, respectively, through at least one of a package, a system board, and a memory module.
6. The impedance adjusting circuit according to claim 5 , wherein said impedance adjusting circuit is included in a memory controller.
7. The impedance adjusting circuit according to claim 1 , wherein said first output buffer includes:
a first pull-up buffer and a first pull-down buffer, said first pull-up buffer and said first pull-down buffer being connected in series between first and second power supplies and receiving a first input signal in common, outputs of said first pull-up buffer and said first pull-down buffer being connected to said first terminal, impedances of said first pull-up buffer and said first pull-down buffer being adjustably controlled; and wherein
said second output buffer includes:
a second pull-up buffer and a second pull-down buffer, said second pull-up buffer and said second pull-down buffer being connected in series between said first and second power supplies and receiving a second input signal in common, outputs of said second pull-up buffer and said second pull-down buffer being connected to said second terminal, impedances of said second pull-up buffer and said second pull-down buffer being adjustably controlled.
8. The impedance adjusting circuit according to claim 5 , wherein the first and second signals output from said first and second output buffers, respectively are complementary data control signals DQS and DQSB, respectively, the data control signals DQS and DQSB being output differentially from said memory in the OCD impedance adjusting drive mode.
9. The impedance adjusting circuit according to claim 5 , wherein the first and second signals output from said first and second output buffers, respectively, are a data signal DQ and a complementary signal DQSB of a data control signal DQS, respectively, the data signal DQ and the signal DQSB being output from said memory in the OCD impedance adjusting mode.
10. The impedance adjusting circuit according to claim 1 , wherein a length of wiring between an output terminal of said first output buffer and said first terminal and a length of wiring between an output terminal of said second output buffer and said second terminal are electrically made equal.
11. The impedance adjusting circuit according to claim 1 , wherein the reference voltage is adjustably controlled.