Apparatus and method for detecting data error
View Patent ↗A semiconductor circuit includes a parity bit adding circuit configured to add a parity bit to a data to be read by a CPU; a register configured to hold the data with the parity bit; and a parity check circuit configured to execute a parity check of said data with said parity bit held in said register, and to issue a parity error interrupt when a parity error is detected. A parity bit inverting circuit inverts said parity bit held in said register in response to completion of said parity check.
1. A semiconductor circuit comprising:
a parity bit adding circuit configured to add a parity bit to a data to be read by a CPU;
a register configured to hold said data with said parity bit;
a parity check circuit configured to execute a parity check of said data with said parity bit held in said register, and to issue a parity error interrupt when a parity error is detected; and
a parity bit inverting circuit configured to invert said parity bit held in said register in response to completion of said parity check at least when the parity error is not detected.
2. The semiconductor circuit according to claim 1 , wherein said parity check circuit supplies an interrupt signal to the CPU in response to an execution result of said parity check.
3. A microcomputer comprising:
a CPU;
a peripheral circuit configured to output a data to be read by said CPU;
a parity bit adding circuit configured to add a parity bit to said data and generates the data with the parity bit;
a register configured to hold the data with the parity bit;
a parity check circuit configured to execute a parity check of the data with the parity bit held by said register; and
a parity bit inverting circuit configured to invert said parity bit held in said register in response to completion of said parity check at least when the parity error is not detected.
4. The microcomputer according to claim 3 , wherein said parity check circuit supplies said CPU with an interrupt signal in response to execution result of the parity check.
5. The microcomputer according to claim 4 , further comprising:
a memory;
a direct memory access controller configured to execute a direct memory access in response to an instruction from said peripheral circuit.
6. An error detecting method comprising:
adding a parity bit to a data to be read by a CPU;
writing said data with said parity bit in a register;
carrying out a parity check of said data with said parity bit; and
inverting said parity bit added to said data in response to an execution completion by said parity check at least when the parity error is not detected.
7. The error detecting method according to claim 6 , further comprising:
supplying an interrupt signal to said CPU in response to execution result of said parity check.
8. A microcomputer comprising:
a CPU;
a memory;
a peripheral circuit being configured to output a data;
a direct memory access controller configured to control a direct memory access to said memory in response to an instruction from said peripheral circuit;
a parity bit adding circuit configured to add a parity bit to said data and generates the data with the parity bit;
a register configured to hold the data with the parity bit;
a parity check circuit configured to execute a parity check of the data with the parity bit held by said register; and
a parity bit inverting circuit configured to invert said parity bit held in said register in response to completion of said parity check at least when the parity error is not detected.