Method of manufacturing semiconductor device having impurity region under isolation region
View Patent ↗In formation of a source/drain region of an NMOS transistor, a gate-directional extension region < 41 a > of an N + block region < 41 > in an N + block resist film < 51 > prevents a well region < 11 > located under the gate-directional extension region < 41 a > from implantation of an N-type impurity. A high resistance forming region, which is the well region < 11 > having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode < 9 >, can be formed as a high resistance forming region <A 2 > narrower than a conventional high resistance forming region <A 1 >. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
1. A method of manufacturing a semiconductor device comprising the steps of:
(a) preparing an SOI substrate formed by a semiconductor substrate, an insulating layer on said semiconductor substrate and a silicon layer on said insulating layer and said silicon layer has a first conductivity type in first, second and third regions;
(b) forming a partial oxide film with thickness not reaching to said insulating layer in a surface of said silicon layer in said second region between said first and third regions;
(b-1) forming a trench not reaching to said insulating layer in a surface of said silicon layer in said second region between said first and third regions;
(b-2) filling said trench by an oxide film;
(b-3) forming a partial oxide film by polishing said oxide film;
(c) forming a gate electrode through a gate oxide film on said surface of said silicon layer in said first region, said gate electrode extending on said partial oxide film in said second region;
(d) introducing a first impurity of a second conductivity type into both ends of said gate electrode in said first region using a first mask layer covering said third region and exposing said first region; and
(e) introducing a second impurity of said first conductivity type into said third region using a second mask layer covering said first region and exposing said third region, wherein
said first mask layer covers said third and second regions and a part of said gate electrode in said second region.
2. The method of manufacturing a semiconductor device according to claim 1 , wherein
said silicon layer includes a fourth region of said second conductivity type different from said first, second and third regions,
in said step (d), said first mask layer covers said fourth region,
in said step (e), said second mask layer exposes said fourth region, and
said second impurity is introduced into said fourth region.
3. A method of manufacturing a semiconductor device comprising the steps of:
(a) preparing an SOI substrate formed by a semiconductor substrate, an insulating layer on said semiconductor substrate and a silicon layer on said insulating layer and said silicon layer has a first conductivity type in first, second and third regions;
(b) forming a partial oxide film with thickness not reaching to said insulating layer in a surface of said silicon layer in said second region between said first and third regions;
(b-1) forming a trench not reaching to said insulating layer in a surface of said silicon layer in said second region between said first and third regions;
(b-2) filling said trench by an oxide film;
(b-3) forming a partial oxide film by polishing said oxide film;
(c) forming a gate electrode through a gate oxide film on said surface of said silicon layer in said first region, said gate electrode extending on said partial oxide film in said second region;
(d) introducing a first impurity of a second conductivity type into both ends of said gate electrode in said first region using a first mask layer covering said third region and exposing said first region; and
(e) introducing a second impurity of said first conductivity type into said third region using a second mask layer covering said first region and exposing said third region, wherein said first mask layer extends from said third region to said second region and covers a part of said gate electrode in said second region.
4. The method of manufacturing a semiconductor device according to claim 3 , wherein
said silicon layer includes a fourth region of said second conductivity type different from said first, second and third regions,
in said step (d), said first mask layer covers said fourth region,
in said step (e), said second mask layer exposes said fourth region, and
said second impurity is introduced into said fourth region.
5. A method of manufacturing a semiconductor device comprising the steps of:
(a) preparing an SOI substrate formed by a semiconductor substrate, an insulating layer on said semiconductor substrate and a silicon layer on said insulating layer and said silicon layer has a first conductivity type in first, second and third regions;
(b) forming a partial oxide film with thickness not reaching to said insulating layer in a surface of said silicon layer in said second region between said first and third regions;
(b-1) forming a trench not reaching to said insulating layer in a surface of said silicon layer in said second region between said first and third regions;
(b-2) filling said trench by an oxide film;
(b-3) forming a partial oxide film by polishing said oxide film;
(c) forming a gate electrode through a gate oxide film on said surface of said silicon layer in said first region, said gate electrode extending on said partial oxide film in said second region;
(d) introducing a first impurity of a second conductivity type into both ends of said gate electrode in said first region using a first mask layer covering said third region and exposing said first region; and
(e) introducing a second impurity of said first conductivity type into said third region using a second mask layer covering said first region and exposing said third region, wherein
said first mask layer covers said partial oxide film and a part of said gate electrode in said second region.
6. The method of manufacturing a semiconductor device according to claim 5 , wherein
said silicon layer includes a fourth region of said second conductivity type different from said first, second and third regions,
in said step (d), said first mask layer covers said fourth region,
in said step (e), said second mask layer exposes said fourth region, and said second impurity is introduced into said fourth region.