Pre-emphasis circuit
View Patent ↗Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, a second parallel-to-serial converter, a mixing circuit and a clock generating circuit. The first parallel-to-serial converter converts parallel data into first serial data, and the second parallel-to-serial converter converts the parallel data into second serial data. The mixing circuit receives the first serial data from the first parallel-to-serial converter and the second serial data from the second parallel-to-serial converter to output a signal emphasizing a change point of the first serial data. The clock generating circuit outputs a first set of clocks made up of clocks having mutually different phases and a second set of clocks made up of clocks having mutually different phases to the first and second parallel-to-serial converters, respectively. The first phase clock of the second set of clocks corresponds to the second phase clock of the first set of clocks.
1. A pre-emphasis circuit comprising:
a first parallel-to-serial converter, receiving parallel data, for converting said parallel data to first serial data for output;
a mixing circuit, receiving said first serial data output from said first parallel-to-serial converter and second serial data delayed by a preset delay time from said first serial data, for generating a signal, an amplitude thereof undergoing pre-emphasis responsive to a transition of said first serial data;
a second parallel-to-serial converter, receiving said parallel data in common with said first parallel-to-serial converter, for converting said parallel data to second serial data for output; and
a circuit for delaying the conversion timing of said second parallel-to-serial converter by said preset delay time from the conversion timing of said first parallel-to-serial converter;
said second serial data delayed by said preset delay time, which is received by said mixing circuit, being generated by said second parallel-to-serial converter, wherein said second serial data is delayed by one clock period from said first serial data.
2. A pre-emphasis circuit comprising:
a first parallel-to-serial converter, receiving parallel data, for converting said parallel data to first serial data for output;
a mixing circuit, receiving said first serial data output from said first parallel-to-serial converter and second serial data delayed by a preset delay time from said first serial data, for generating a signal, an amplitude thereof undergoing pre-emphasis responsive to a transition of said first serial data;
a second parallel-to-serial converter, receiving said parallel data in common with said first parallel-to-serial converter, for converting said parallel data to second serial data for output; and
a circuit for delaying the conversion timing of said second parallel-to-serial converter by said preset delay time from the conversion timing of said first parallel-to-serial converter;
said second serial data delayed by said preset delay time, which is received by said mixing circuit, being generated by said second parallel-to-serial converter,
wherein said circuit for delaying the conversion timing of said second parallel-to-serial converter includes a clock generating circuit for generating and supplying a first multi-phase clock signal composed of clock signals having mutually different phases and a second multi-phase clock signal composed of clock signals having mutually different phases to said first parallel-to-serial converter and said second parallel-to-serial converter, respectively,
the first phase clock of said second multi-phase clock signal being shifted from the first phase clock of said first multi-phase clock signal by a time corresponding to said preset delay time.
3. A pre-emphasis circuit comprising:
a first parallel-to-serial converter, receiving parallel data, for converting said parallel data to first serial data for output;
a mixing circuit, receiving said first serial data output from said first parallel-to-serial converter and second serial data delayed by a preset delay time from said first serial data, for generating a signal, an amplitude thereof undergoing pre-emphasis responsive to a transition of said first serial data;
a second parallel-to-serial converter, receiving said parallel data in common with said first parallel-to-serial converter, for converting said parallel data to second serial data for output; and
a circuit for delaying the conversion timing of said second parallel-to-serial converter by said preset delay time from the conversion timing of said first parallel-to-serial converter;
said second serial data delayed by said preset delay time, which is received by said mixing circuit, being generated by said second parallel-to-serial converter,
wherein at least one of said first and second parallel-to-serial converters includes a plurality of switches placed in juxtaposition; said switches receiving corresponding ones of a plurality of bit data forming said parallel data, as inputs, and having output ends connected in common; said switches receiving corresponding ones of said first and second multi-phase clocks for being turned on to output the bit data supplied thereto when said clock signals are of a first value and for being turned off when said clock signals are of a second value.
4. A pre-emphasis circuit comprising:
a first parallel-to-serial converter, receiving parallel data, for converting said parallel data to first serial data for output;
a mixing circuit, receiving said first serial data output from said first parallel-to-serial converter and second serial data delayed by a preset delay time from said first serial data, for generating a signal, an amplitude thereof undergoing pre-emphasis responsive to a transition of said first serial data;
a second parallel-to-serial converter, receiving said parallel data in common with said first parallel-to-serial converter, for converting said parallel data to second serial data for output; and
a circuit for delaying the conversion timing of said second parallel-to-serial converter by said preset delay time from the conversion timing of said first parallel-to-serial converter;
said second serial data delayed by said preset delay time, which is received by said mixing circuit, being generated by said second parallel-to-serial converter,
wherein, if, under the condition that said mixing circuit is outputting a signal of a pre-emphasized amplitude, the logic value of the next following serial data is not changed, said mixing circuit outputs a signal of a de-emphasized amplitude.
5. A pre-emphasis circuit comprising:
a first parallel-to-serial converter, receiving parallel data, for converting said parallel data to first serial data for output;
a mixing circuit, receiving said first serial data output from said first parallel-to-serial converter and second serial data delayed by a preset delay time from said first serial data, for generating a signal, an amplitude thereof undergoing pre-emphasis responsive to a transition of said first serial data;
a second parallel-to-serial converter, receiving said parallel data in common with said first parallel-to-serial converter, for converting said parallel data to second serial data for output; and
a circuit for delaying the conversion timing of said second parallel-to-serial converter by said preset delay time from the conversion timing of said first parallel-to-serial converter;
said second serial data delayed by said preset delay time, which is received by said mixing circuit, being generated by said second parallel-to-serial converter,
wherein said mixing circuit includes
a first buffer and a second buffer for receiving said first serial data and a signal corresponding to inversion of bit data of said second serial data, respectively;
said first and second buffers having outputs connected in common;
said second buffer having an output impedance higher than an output impedance of said first buffer or having an output impedance variably controlled by a control signal controlling the emphasis.
6. A semiconductor device including
a pre-emphasis circuit which comprises:
first and second parallel-to-serial converters, receiving parallel data in common, for converting said parallel data into serial data, respectively;
a circuit for delaying the conversion timing of said second parallel-to-serial converter by a preset delay time from the conversion timing of said first parallel-to-serial converter, so that said second parallel-to-serial converter outputs second serial data delayed from first serial data output from said first parallel-to-serial converter, wherein said second serial data is delayed by one clock period from said first serial data; and
a circuit, receiving said first and second serial data output from said first and second parallel-to-serial converters, for generating a signal obtained on emphasizing an amplitude at a change point of said first serial data for output, based on said first and second serial data.
7. A semiconductor device including
a pre-emphasis circuit which comprises:
first and second parallel-to-serial converters, receiving parallel data in common, for converting said parallel data into serial data, respectively;
a circuit for delaying the conversion timing of said second parallel-to-serial converter by a preset delay time from the conversion timing of said first parallel-to-serial converter, so that said second parallel-to-serial converter outputs second serial data delayed from first serial data output from said first parallel-to-serial converter; and
a circuit, receiving said first and second serial data output from said first and second parallel-to-serial converters, for generating a signal obtained on emphasizing an amplitude at a change point of said first serial data for output, based on said first and second serial data,
wherein, if, under the condition that the pre-emphasis circuit is outputting a signal of the emphasized amplitude, the logic value of the next following first serial data is not changed, said pre-emphasis circuit outputs a signal with a deemphasized amplitude.
8. A serial interfacing circuit comprising:
a clock and data recovery circuit for extracting a clock signal and a data signal from received serial data;
a circuit for converting data from said clock and data recovery circuit into parallel data, based on a synchronizing clock signal extracted from said clock and data recovery circuit; and
a pre-emphasis circuit for outputting transmission data over a transmission line, the pre-emphasis circuit comprising:
a first parallel-to-serial converter, receiving parallel data, for converting said parallel data to first serial data for output;
a mixing circuit, receiving said first serial data output from said first parallel-to-serial converter and second serial data delayed by a preset delay time from said first serial data, for generating a signal, an amplitude thereof undergoing pre-emphasis responsive to a transition of said first serial data;
a second parallel-to-serial converter, receiving said parallel data in common with said first parallel-to-serial converter, for converting said parallel data to second serial data for output; and
a circuit for delaying the conversion timing of said second parallel-to-serial converter by said preset delay time from the conversion timing of said first parallel-to-serial converter;
said second serial data delayed by said preset delay time, which is received by said mixing circuit, being generated by said second parallel-to-serial converter.