Semiconductor device and method of fabricating the same
View Patent ↗A method for fabricating a semiconductor device, including forming a gate insulating layer and a gate electrode on a substrate; forming insulating layer sidewalls at sides of the gate electrode; forming source/drain regions in surface portions of the substrate that are located, respectively, at sides of the gate electrode; forming a conductive silicide layer on the entire surface of the substrate; and selectively removing the silicide layer from areas other than the gate electrode and the source/drain regions of the substrate. The conductive silicide layer may be made by forming a silicon layer on an entire surface of the substrate; forming a conductive layer on the silicon layer; and thermal-processing the substrate such that the conductive layer reacts with the silicon layer.
1. A method for fabricating a semiconductor device, the method comprising:
forming a gate insulating layer and a gate electrode on a substrate;
forming insulating layer sidewalls at sides of the gate electrode;
forming source/drain regions in surface portions of the substrate that are located, respectively, at opposed sides of the gate electrode;
forming a silicon layer on an entire surface of the substrate including the gate electrode by injecting a gas that includes silicon into a chamber;
forming a conductive layer on the entire surface of the substrate including the silicon layer;
forming a conductive silicide layer on the entire surface of the substrate by thermal-processing the substrate such that the conductive layer reacts with the silicon layer; and
selectively removing the silicide layer that does not correspond to the gate electrode and the source/drain regions of the substrate.
2. The method according to claim 1 , wherein the gas that includes silicon comprises SiH 4 .
3. The method according to claim 1 , further comprising, before forming the silicon layer, heating the substrate to a temperature of 250˜400° C.
4. The method according to claim 1 , wherein the silicon layer is formed at a deposition temperature of about 350°.
5. The method according to claim 1 , wherein the conductive layer has a thickness of 50˜300 Å.
6. The method according to claim 3 , further comprising, before forming the silicon layer, heating the substrate to about 350° C.
7. The method according to claim 1 , wherein the thermal processing is performed at a temperature of 300˜500° C.
8. The method according to claim 7 , wherein the thermal processing is performed for a time of from 10 seconds to about 2 minutes.
9. The method according to claim 1 , wherein the conductive layer is formed at a temperature of 100˜300° C.
10. The method according to claim 1 , further comprising forming a capping layer comprising Ti, TiN, or a Ti/TiN bilayer on the conductive layer.
11. The method according to claim 10 , wherein the capping layer has a thickness of 100˜400 Å.
12. The method according to claim 1 , wherein the conductive layer comprises a material selected from the group consisting of nickel, cobalt, titanium, tungsten, tantalum, and molybdenum.
13. The method according to claim 12 , wherein the conductive silicide layer comprises Nickel (Ni) and Silicon (Si) in a ratio of about 1:1.
14. The method of claim 1 , wherein the gate electrode comprises polysilicon.
15. The method of claim 1 , wherein forming the insulating layer sidewalls comprises depositing an insulating material on an entire surface of the substrate, the selectively etching the insulating material.
16. The method of claim 1 , wherein forming the source/drain regions comprises implanting n-type or p-type impurities in surface portions of the substrate that are located, respectively, at opposed sides of the gate electrode.
17. The method of claim 16 , wherein forming the source/drain regions further comprises thermal processing at a temperature of about 1000-1050° C. after implanting n-type or p-type impurities.
18. The method of claim 1 , further comprising after forming the gate electrode and insulating sidewalls, washing with SC1 solution, HF solution, or DHF solution.
19. The method of claim 1 , wherein forming the conductive layer comprises depositing a conductive material by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
20. The method of claim 1 , wherein selectively removing the silicide layer comprises wet etching the silicide layer.