Method of making vertical transistor structures having vertical-surrounding-gates with self-aligned features
The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silicon pillars used to form the vertical-surrounding gate field effect transistor structure for use in the manufacture of semiconductor devices.
1. A method of forming a semiconductor assembly having vertical transistor structures comprising:
forming columns of trench isolation material in a silicon substrate;
forming circular patterned hard mask material in circular holes in an insulation material overlying the silicon substrate;
forming partial silicon pillars by removing an upper portion of the silicon substrate while using the hard mask material as an etching mask;
forming nitride spacers on sidewalls of the partial silicon pillars;
with the hard mask material in place, etching the trench isolation material and the silicon substrate to a desired depth to form silicon pillars, each having a defined channel length determined by extending the partial silicon pillars in a vertical direction below the nitride spacers;
forming a gate dielectric on an exposed portion of the silicon pillars below the nitride spacers;
depositing a conformal polysilicon material over the silicon substrate, the trench isolation material, the hard mask material, the nitride spacers and the transistor gate dielectric;
forming a silicon pillar isolation material over the conformal polysilicon material;
planarizing the conformal polysilicon material and the silicon pillar isolation material;
recessing the conformal polysilicon material down to a base of the nitride spacers to form a vertical-surrounding-gate of the vertical transistor structures;
forming an anti-reflective coating over the conformal polysilicon material and silicon pillar isolation material;
forming conductors to connect to a series of vertical-surrounding-gates;
depositing an insulation material over the polysilicon material and silicon pillar isolation material; and
removing the hard mask material to create a surface for a vertical-surrounding-gate source contact.
2. The method of claim 1 , wherein the insulation material is a tetra-ethyl-ortho-silicate (TEOS) oxide.
3. The method of claim 1 , wherein the circular patterned hard mask material is nitride.
4. The method of claim 1 , wherein the forming of the partial silicon pillars comprises an etch that defines approximately one half the total length of the silicon pillars.
5. The method of claim 1 , further comprising etching a horizontal component of the exposed portions of the silicon pillars below the nitride spacers to approximately the width of the nitride spacers.
6. The method of claim 1 , wherein the silicon pillar isolation material is a material selected from the group consisting essentially of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or a spin on dielectric (SOD).
7. The method of claim 1 , wherein the planarizing the conformal polysilicon material and the silicon pillar isolation material comprises chemical-mechanical planarization (CMP).
8. The method of claim 1 , wherein the recessing of the conformal polysilicon material continues below the base of the nitride spacers.
9. The method of claim 1 , wherein the insulation material to fill any gaps around the silicon pillars is a material selected from the group consisting essentially of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or a spin on dielectric (SOD).
10. The method of claim 1 , wherein exposing the upper surface of the silicon pillars to create a surface for a vertical-surrounding-gate source contact comprises chemical-mechanical planarization (CMP).
11. A method of forming vertical transistor structures for a semiconductor assembly comprising:
forming columns of trench isolation material in a silicon substrate;
forming circular patterned hard mask material in circular holes in an insulation material overlying the silicon substrate;
forming partial silicon pillars by removing an upper portion of the silicon substrate while using the hard mask material as an etching mask;
forming nitride spacers on sidewalls of the partial silicon pillars;
with the hard mask material in place, etching the trench isolation material and the silicon substrate to a desired depth to form silicon pillars, each having a defined channel length determined by extending the partial silicon pillars in a vertical direction below the nitride spacers;
etching a horizontal component of exposed portions of the silicon pillars below the nitride spacers to approximately the width of nitride spacers;
forming a gate dielectric on an exposed portion of the silicon pillars below the nitride spacers;
depositing a conformal polysilicon material over the silicon substrate, the trench isolation material, the hard mask material, the nitride spacers and the transistor gate dielectric;
forming a silicon pillar isolation material over the conformal polysilicon material;
planarizing the conformal polysilicon material and the silicon pillar isolation material;
recessing the conformal polysilicon material down to a base of the nitride spacers to form a vertical-surrounding-gate of the vertical transistor structures;
forming an anti-reflective coating over the conformal polysilicon material and silicon pillar isolation material;
forming conductors to connect to a series of vertical-surrounding-gates;
etching the polysilicon material to form the conductors from the polysilicon gate material;
depositing an insulation material to fill any gaps around the silicon pillars; and
exposing an upper surface of the silicon pillars to create a surface for a vertical-surrounding-gate source contact.
12. The method of claim 11 , wherein the insulation material is a tetra-ethyl-ortho-silicate (TEOS) oxide.
13. The method of claim 11 , wherein the circular patterned hard mask material is nitride.
14. The method of claim 11 , wherein the forming of the partial silicon pillars comprises an etch that defines approximately one half the total length of the silicon pillars.
15. The method of claim 11 , wherein the silicon pillar isolation material is a material selected from the group consisting essentially of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or a spin on dielectric (SOD).
16. The method of claim 11 , wherein the planarizing the conformal polysilicon material and the silicon pillar isolation material comprises chemical-mechanical planarization (CMP).
17. The method of claim 11 , wherein the recessing of the conformal polysilicon material continues below the base of the nitride spacers.
18. The method of claim 11 , wherein the insulation material to fill any gaps around the silicon pillars is a material selected from the group consisting essentially of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or a spin on dielectric (SOD).
19. The method of claim 11 , wherein exposing the upper surface of the silicon pillars to create a surface for a vertical-surrounding-gate source contact comprises chemical-mechanical planarization (CMP).
20. A method of forming a semiconductor assembly having memory cells with vertical transistor structures comprising:
forming columns of trench isolation material in a silicon substrate;
forming circular patterned hard mask material in circular holes in an insulation material overlying the silicon substrate;
forming partial silicon pillars by removing an upper portion of the silicon substrate while using the hard mask material as an etching mask;
forming nitride spacers on sidewalls of the partial silicon pillars;
with the hard mask material in place, etching the trench isolation material and the silicon substrate to a desired depth to form silicon pillars, each having a defined channel length determined by extending the partial silicon pillars in a vertical direction below the nitride spacers;
forming a gate dielectric on an exposed portion of the silicon pillars below the nitride spacers;
depositing a conformal polysilicon material over the silicon substrate, the trench isolation material, the hard mask material, the nitride spacers and the transistor gate dielectric;
forming a silicon pillar isolation material over the conformal polysilicon material;
planarizing the conformal polysilicon material and the silicon pillar isolation material;
recessing the conformal polysilicon material down to a base of the nitride spacers to form a vertical-surrounding-gate of the vertical transistor structures;
forming an anti-reflective coating over the conformal polysilicon material and silicon pillar isolation material;
forming conductors to connect to a series of vertical-surrounding-gates;
depositing an insulation material over the conformal polysilicon material and silicon pillar isolation material;
exposing an upper surface of the silicon pillars to create a surface for a vertical-surrounding-gate source contact; and
forming a capacitor structure connecting the silicon pillars at the vertical-surrounding-gate source contact.
21. The method of claim 20 , wherein the insulation material is a tetra-ethyl-ortho-silicate (TEOS) oxide.
22. The method of claim 20 , wherein the circular patterned hard mask material is nitride.
23. The method of claim 20 , wherein the forming of the partial silicon pillars comprises an etch that defines approximately one half the total length of the silicon pillars.
24. The method of claim 20 , further comprising etching a horizontal component of the exposed portions of the silicon pillars below the nitride spacers to approximately the width of the nitride spacers.
25. The method of claim 20 , wherein the silicon pillar isolation material is a material selected from the group consisting essentially of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or a spin on dielectric (SOD).
26. The method of claim 20 , wherein the planarizing the conformal polysilicon material and the silicon pillar isolation material comprises chemical-mechanical planarization (CMP).
27. The method of claim 20 , wherein the recessing of the conformal polysilicon material continues below the base of the nitrides spacers.
28. The method of claim 20 , wherein the insulation material to fill any gaps around the silicon pillars is a material selected from the group consisting essentially of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or a spin on dielectric (SOD).
29. The method of claim 20 , wherein exposing the upper surface of the silicon pillars to create a surface for a vertical-surrounding-gate source contact comprises chemical-mechanical planarization (CMP).
30. A method of forming a semiconductor assembly having vertical transistor structures comprising:
forming partial silicon pillars by etching into a silicon substrate having isolation regions therein, to define a vertical transistor source for each vertical transistor structure;
forming nitride spacers on sidewalls of each vertical transistor source;
extending the overall length of the silicon pillars by etching further into the silicon substrate to a desired depth below the nitride spacers, the extended length of the silicon pillars defining a vertical transistor channel length for each vertical transistor structure;
forming a gate dielectric on the extended length of the silicon pillars below the nitride spacers;
depositing a conformal polysilicon material over the silicon substrate, the nitride spacers and the transistor gate dielectric;
forming a silicon pillar isolation material over the conformal polysilicon material;
etching the conformal polysilicon material and the silicon pillar isolation material to a base of the nitride spacers;
recessing the conformal polysilicon material to the base of the nitride spacers to form a vertical-surrounding-gate of the vertical transistor structures such that the distance between an active area of the silicon pillars and any portion of the recessed conformal polysilicon material that may reside along the nitride spacers is great enough to prevent an extension of the vertical transistor channel length of each vertical transistor structure.
31. The method of claim 30 , wherein the etching of the partial silicon pillars comprises an etch that defines approximately one half the total length of the silicon pillars.
32. The method of claim 30 , further comprising etching a horizontal component of the exposed portions of the silicon pillars below the nitride spacers to approximately the width of the nitride spacers.
33. The method of claim 30 , wherein the silicon pillar isolation material is a material selected from the group consisting essentially of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or a spin on dielectric (SOD).
34. The method of claim 30 , wherein the etching the conformal polysilicon material and the silicon pillar isolation material comprises chemical-mechanical planarization (CMP).
35. The method of claim 30 , wherein the recessing of the conformal polysilicon material continues below the base of the nitride spacers.
36. A method of forming a semiconductor assembly with vertical transistor structures comprising:
forming partial silicon pillars by etching into a silicon substrate having isolation regions therein, to define a vertical transistor source for each vertical transistor structure;
forming nitride spacers on sidewalls of each vertical transistor source;
extending the overall length of the silicon pillars by etching further into the silicon substrate to a desired depth below the nitride spacers, the extended length of the silicon pillars defining a vertical transistor channel length for each vertical transistor structure;
forming a gate dielectric on the extended length of the silicon pillars below the nitride spacers;
depositing a conformal polysilicon material over the silicon substrate, the nitride spacers and the transistor gate dielectric;
forming a silicon pillar isolation material over the conformal polysilicon material;
etching the conformal polysilicon material and the silicon pillar isolation material to a base of the nitride spacers;
recessing the conformal polysilicon material to the base of the nitride spacers to form a vertical-surrounding-gate of the vertical transistor structures;
wherein the distance between an active area of the silicon pillars and any portion of the recessed conformal polysilicon material present along the nitride spacers is great enough to prevent an inversion of the active area during an active state of a vertical transistor structure.
37. The method of claim 36 , wherein the etching of the partial silicon pillars comprises an etch that defines approximately one half the total length of the silicon pillars.
38. The method of claim 36 , further comprising etching a horizontal component of the exposed portions of the silicon pillars below the nitride spacers to approximately the width of the nitride spacers.
39. The method of claim 36 , wherein the silicon pillar isolation material is a material selected from the group consisting essentially of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or a spin on dielectric (SOD).
40. The method of claim 36 , wherein the etching the conformal polysilicon material and the silicon pillar isolation material comprises chemical-mechanical planarization (CMP).
41. The method of claim 36 , wherein the recessing of the conformal polysilicon material continues below the base of the nitride spacers.
42. A method of forming a semiconductor assembly having memory cells with vertical transistor structures comprising:
forming partial silicon pillars by etching into a silicon substrate having isolation regions therein, to define a vertical transistor source for each vertical transistor structure;
forming nitride spacers on sidewalls of each vertical transistor source;
extending the overall length of the silicon pillars by etching further into the silicon substrate to a desired depth below the nitride spacers, the extended length of the silicon pillars defining a vertical transistor channel length for each vertical transistor structure;
forming a gate dielectric on the extended length of the silicon pillars below the nitride spacers;
depositing a conformal polysilicon material over the silicon substrate, the nitride spacers and the transistor gate dielectric;
forming a silicon pillar isolation material over the conformal polysilicon material;
etching the conformal polysilicon material and the silicon pillar isolation material to a base of the nitride spacers;
recessing the conformal polysilicon material to the base of the nitride spacers to form a vertical-surrounding-gate of the vertical transistor structures such that the distance between an active area of the silicon pillars and any portion of the recessed conformal polysilicon material present along the nitride spacers is great enough to prevent an inversion of the active area during an active state of a vertical transistor structure;
forming an anti-reflective coating over the conformal polysilicon material and silicon pillar isolation material;
forming conductors to connect to a series of vertical-surrounding-gates;
depositing an insulation material around the silicon pillars;
exposing an upper surface of the silicon pillars to create a surface for a vertical-surrounding-gate source contact; and
forming a capacitor structure connecting the silicon pillars at the vertical-surrounding-gate source contact.
43. The method of claim 42 , wherein the etching of the partial silicon pillars comprises an etch that defines approximately one half the total length of the silicon pillars.
44. The method of claim 42 , further comprising etching a horizontal component of the exposed portions of the silicon pillars below the nitride spacers to approximately the width of the nitride spacers.
45. The method of claim 42 , wherein the silicon pillar isolation material is a material selected from the group consisting essentially of borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or a spin on dielectric (SOD).
46. The method of claim 42 , wherein the etching the conformal polysilicon material and the silicon pillar isolation material comprises chemical-mechanical planarization (CMP).
47. The method of claim 42 , wherein the recessing of the conformal polysilicon material continues below the base of the nitride spacers.