In-pixel kTC noise suppression using circuit techniques
View Patent ↗A circuit and method for reducing kTC noise in CMOS imagers while minimizing power dissipation is disclosed. Correlated double sampling (CDS) is performed within each pixel such that the reset voltage and the integration voltage are sampled and stored within the pixel until the voltages are forwarded to a differential amplifier for subtraction.
1. An active pixel sensor, comprising:
a plurality of pixels, wherein each of said pixels comprises:
a reset portion for resetting a photosensitive element of said pixel;
a capacitor coupled between a clamp switch and a first source follower transistor of said reset portion, said capacitor being configured to store a reset voltage of said photosensitive element;
a column bus coupled to a storage node for receiving said reset voltage level;
a gate of a second source follower transistor coupled to said capacitor and said clamp switch, said second source follower transistor switchably coupling said capacitor to said column bus;
a first source/drain terminal of a load transistor coupled to ground;
a second source/drain terminal of said load transistor coupled to said first source follower transistor and said storage capacitor; and
a selection transistor coupled between said load transistor and ground for controlling selection of said reset portion.
2. An active pixel sensor, comprising:
a plurality of pixels, wherein each of said pixels comprises:
a reset portion for resetting a photosensitive element of said pixel;
a capacitor coupled between a clamp switch and a first source follower transistor of said reset portion, said capacitor being configured to store a reset voltage of said photosensitive element;
a column bus coupled to a storage node for receiving said reset voltage level;
a gate of a second source follower transistor coupled to said capacitor and said clamp switch, said second source follower transistor switchably coupling said capacitor to said column bus; and
a switch switchably coupling said first source follower transistor and said clamp capacitor to a second column bus for separately reading out said reset voltage.
3. A semiconductor chip, comprising:
an active pixel sensor, said active pixel sensor comprising:
a plurality of pixels, wherein each of said pixels comprises:
a reset portion for resetting a photosensitive element of said pixel; and
a capacitor coupled between a clamp switch and a first source follower transistor of said reset portion, said capacitor being configured to store a reset voltage of said photosensitive element;
a column bus coupled to a storage node for receiving said reset voltage level;
a gate of a second source follower transistor coupled to said capacitor and said clamp switch, said second source follower transistor switchably coupling said capacitor to said column bus;
a first source/drain terminal of a load transistor coupled to ground;
a second source/drain terminal of said load transistor coupled to said first source follower transistor and said storage capacitor; and
a selection transistor coupled between said load transistor and ground for controlling selection of said reset portion.
4. A semiconductor chip, comprising:
an active pixel sensor, said active pixel sensor comprising:
a plurality of pixels, wherein each of said pixels comprises:
a reset portion for resetting a photosensitive element of said pixel; and
a capacitor coupled between a clamp switch and a first source follower transistor of said reset portion, said capacitor being configured to store a reset voltage of said photosensitive element;
a column bus coupled to a storage node for receiving said reset voltage level;
a gate of a second source follower transistor coupled to said capacitor and said clamp switch, said second source follower transistor switchably coupling said capacitor to said column bus; and
a switch switchably coupling said first source follower transistor and said clamp capacitor to a second column bus for separately reading out said reset voltage.
5. A processor system, comprising:
a processor; and
an imager device coupled to said processor for sending signals to said processor, said imager device comprising:
a plurality of pixels, wherein each of said pixels comprises:
a reset portion for resetting a photosensitive element of said pixel;
a capacitor coupled between a clamp switch and a first source follower transistor of said reset portion, said capacitor being configured to store a reset voltage of said photosensitive element;
a column bus coupled to said storage node for receiving said reset voltage level;
a gate of a second source follower transistor coupled to said capacitor and said clamp switch, said second source follower transistor switchably coupling said capacitor to said column bus;
a first source/drain terminal of a load transistor coupled to ground;
a second source/drain terminal of said load transistor coupled to said first source follower transistor and said storage capacitor; and
a selection transistor coupled between said load transistor and ground for controlling selection of said reset portion.
6. A processor system, comprising:
a processor; and
an imager device coupled to said processor for sending signals to said processor, said imager device comprising:
a plurality of pixels, wherein each of said pixels comprises:
a reset portion for resetting a photosensitive element of said pixel;
a capacitor coupled between a clamp switch and a first source follower transistor of said reset portion, said capacitor being configured to store a reset voltage of said photosensitive element;
a column bus coupled to said storage node for receiving said reset voltage level;
a gate of a second source follower transistor coupled to said capacitor and said clamp switch, said second source follower transistor switchably coupling said capacitor to said column bus; and
a switch switchably coupling said first source follower transistor and said clamp capacitor to a second column bus for separately reading out said reset voltage.