IP Library Granted Patent US 7,678,687
Granted Patent B2
US 7,678,687 · App. 11/496,399 · Granted Mar 16, 2010

Method for manufacturing semiconductor device and semiconductor device

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Quick Facts
Patent No.
US 7,678,687
App. No.
11/496,399
Granted
Mar 16, 2010
Kind
B2
Abstract

In a method for manufacturing a semiconductor device, insulation resistance of the porous film is stabilized, and leakage current between adjacent interconnects provides an improved reliability in signal propagation therethrough. The method includes: sequentially forming over a semiconductor substrate a porous film and a patterned resist film; forming a concave exposed surface of the substrate; forming a non-porous film covering the interior wall of the concave portion and the porous film; selectively removing the non-porous film from the bottom of the concave portion and the non-porous film by anisotropic etch; forming a barrier metal film covering the porous film and the interior wall; and forming a metallic film on the barrier metal film to fill the concave portion. The anisotropic etch process uses an etching gas with mixing ratio MR, 45≦MR≦100, where MR=((gaseous “nitrogen” containing compound)+(inert gas))/(gaseous “fluorine” containing compound).

Claims (28)

1. A method for manufacturing a semiconductor device, comprising:

forming an etching stopper on a semiconductor substrate;

forming a porous film over said semiconductor substrate and said etching stopper;

forming a resist film having a predetermined pattern over said porous film;

forming a concave portion with a bottom thereof being an exposed surface of said etching stopper by etching said porous film through a mask of said resist film;

forming a nonporous film so as to cover a whole of an interior wall of said concave portion and the surface of said porous film;

selectively removing a portion of said nonporous film formed on the bottom of said concave portion, a portion of said non-porous film located on said porous film and a portion of said etching stopper by an anisotropic etch process to expose said semiconductor substrate;

forming a barrier metal film so as to cover said porous film and the interior wall of said concave portion having said non-porous film on the side wall thereof; and

forming a metallic film on said barrier metal film to fill said concave portion and then partially removing portions of said barrier metal film and said metallic film that are outside of said concave portion, thereby partially leaving the barrier metal film and the metallic film only in said concave portion,

wherein, in said selectively removing said non-porous film, the anisotropic etch process is conducted by employing an etching gas having a mixing ratio within a range of equal to or more than 45 and equal to or less than 100, said mixing ratio being represented by a formula:

((gaseous “nitrogen” containing compound)+(inert gas))/(gaseous “fluorine” containing compound).

2. The method for manufacturing the semiconductor device according to claim 1 , wherein said gaseous “nitrogen” containing compound is N 2 gas.

3. The method for manufacturing the semiconductor device according to claim 1 , wherein said inert gas is Ar gas.

4. The method for manufacturing the semiconductor device according to claim 1 , wherein said gaseous “fluorine” containing compound is CF 4 gas.

5. The method for manufacturing the semiconductor device according to claim 1 , wherein, in said selectively removing said nonporous film, the anisotropic etch is conducted under a condition where a degree of vacuum is within a range of equal to or more than 1 mTorr and less than 10 mTorr.

6. The method for manufacturing the semiconductor device according to claim 1 , wherein said anisotropic etch process is a plasma etch process.

7. The method for manufacturing the semiconductor device according to claim 1 , wherein said forming the nonporous film includes forming the nonporous film so as to cover whole of the interior wall of said concave portion and the surface of said porous film by a plasma-enhanced chemical vapor deposition (PECVD) process.

8. The method for manufacturing the semiconductor device according to claim 1 , wherein said forming said barrier metal film includes forming said barrier metal film by an atomic layer deposition (ALD) process.

9. A method for manufacturing a semiconductor device, comprising in order:

forming a porous film over a semiconductor substrate;

forming a resist film having a predetermined pattern over said porous film;

forming a concave portion having a bottom thereof being an exposed surface of said semiconductor substrate by etching said porous film through a mask of said resist film;

forming a nonporous film containing a methyl group so as to cover an entire interior wall of said concave portion and a surface of said porous film;

selectively removing a portion of said non-porous film formed on a bottom of said concave portion and a portion of said nonporous film located on said porous film by an anisotropic etch process;

forming a barrier metal film so as to cover said porous film and the interior wall of said concave portion having said non-porous film on the side wall thereof; and

forming a metallic film on said barrier metal film to fill said concave portion and then partially removing portions of said barrier metal film and said metallic film that are outside of said concave portion, thereby partially leaving the barrier metal film and the metallic film only in said concave portion,

wherein, in said selectively removing said nonporous film, the anisotropic etch process is conducted by employing an etching gas having a mixing ratio within a range of equal to or more than 45 and equal to or less than 100, said mixing ratio being represented by a formula: (N 2 +Ar 2 /CF 4 )

10. The method for manufacturing the semiconductor device according to claim 9 , wherein, in said forming said nonporous film, the nonporous film is formed under a condition where a temperature is equal to or less than 500 degree C.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Nov 4, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025311/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2006
From: FURUYA, AKIRA
To: NEC ELECTRONICS CORPORATION
Reel/Frame 018146/0406 →