Interface circuit

1. An interface circuit, comprising:

a first synchronizing circuit for synchronizing a data signal that is synchronized with a strobe signal having a delay equal to or more than a predetermined period with respect to a reference clock, with the reference clock;

a second synchronizing circuit for synchronizing a data signal that is synchronized with a strobe signal having a delay less than the predetermined period with respect to the reference clock, with the reference clock;

a delay determining circuit for outputting a determination signal based on a result of measuring a delay of the strobe signal relative to the reference clock;

a delay determination setting circuit for outputting a path setting signal that designates one of the first synchronizing circuit and the second synchronizing circuit based on a preset value; and

a delay selecting circuit for selecting and outputting an output value of one of the first synchronizing circuit and the second synchronizing circuit based on one of the determination signal and the path setting signal.

2. The interface circuit according to claim 1 , wherein the delay determination setting circuit further outputs a power control signal for putting an unused one of the first synchronizing circuit and the second synchronizing circuit into a suspend mode.

3. The interface circuit according to claim 1 , wherein the delay determination setting circuit outputs a selection signal for setting which one of the first synchronizing circuit and the second synchronizing circuit is used based on the determination signal in place of the path setting signal.

4. The interface circuit according to claim 1 , wherein a data signal synchronous with a strobe signal having a large delay relative to the reference clock synchronized by the first synchronizing circuit and a data signal synchronous with a strobe signal having a small delay relative to the reference clock synchronized by the second synchronizing circuit are output at substantially the same timing.

5. The interface circuit according to claim 1 , wherein the delay determining circuit determines a delay of the strobe signal based on the reference clock.

6. The interface circuit according to claim 1 , wherein the delay determining circuit determines that a delay is small if a phase difference between the strobe signal and the reference clock is less than 180° and that a delay is large if the phase difference is 180° or more.

7. The interface circuit according to claim 1 , wherein the interface circuit, a CPU, and a memory controller are mounted onto the same semiconductor substrate.

8. The interface circuit according to claim 1 , wherein the interface circuit is an interface connected with a memory controller and a DDR-SDRAM.

9. An interface circuit, comprising:

a first synchronizing circuit for synchronizing a data signal that is synchronized with a strobe signal having a delay equal to or more than a predetermined period with respect to a reference clock, with the reference clock;

a second synchronizing circuit for synchronizing a data signal that is synchronized with a strobe signal having a delay less than the predetermined period with respect to the reference clock, with the reference clock;

a delay determining circuit for outputting a determination signal based on a result of measuring a delay of the strobe signal relative to the reference clock; and

a delay selecting circuit for selecting and outputting an output value of one of the first synchronizing circuit and the second synchronizing circuit based on one of the determination signal and the path setting signal.

10. The interface circuit according to claim 9 , further comprising:

a delay determination setting circuit for outputting a path setting signal that designates one of the first synchronizing circuit and the second synchronizing circuit based on a preset value.

11. The interface circuit according to claim 9 , wherein the delay determination setting circuit further outputs a power control signal for putting an unused one of the first synchronizing circuit and the second synchronizing circuit into a suspend node.

12. The interface circuit according to claim 9 , wherein the delay determination setting circuit outputs a selection signal for setting which one of the first synchronizing circuit and the second synchronizing circuit is used based on the determination signal in place of the path setting signal.

13. The interface circuit according to claim 9 , wherein a data signal synchronous with a strobe signal having a large delay relative to the reference clock synchronized by the first synchronizing circuit and a data signal synchronous with a strobe signal having a small delay relative to the reference clock synchronized by the second synchronizing circuit are output at substantially the same timing.

14. The interface circuit according to claim 9 , wherein the delay determining circuit determines a delay of the strobe signal based on the reference clock.

15. The interface circuit according to claim 9 , wherein the delay determining circuit determines that a delay is small if a phase difference between the strobe signal and the reference clock is less than 180° and that a delay is large if the phase difference is 180° or more.

16. The interface circuit according to claim 9 , wherein the interface circuit, a CPU, and a memory controller are mounted onto the same semiconductor substrate.

17. The interface circuit according to claim 9 , wherein the interface circuit is an interface connected with a memory controller and a DDR-SDRAM.