Output buffer circuit

1. An output buffer circuit receiving a data signal to be output and having a de-emphasis function in which an amplitude of an output signal is emphasized at a time of transition when a logic value of the data signal changes and the emphasized amplitude of the output signal is attenuated at a time of non-transition subsequent to the transition when the data signal has a logic value same as that immediately after the transition, said output buffer circuit comprising:

a circuit receiving a control signal for performing control, when the control signal is of a value indicating an amplitude margin test mode, so as to set the amplitude of the output signal at the time of the transition to be the same as the amplitude at the time of the non-transition and to output the output signal of the amplitude smaller than an amplitude at a time of a normal operation.

2. The output buffer circuit according to claim 1 , comprising:

a first output buffer for receiving the data signal, for output;

a second output buffer having an output connected in common with an output of said first output buffer;

a delay circuit for receiving the data signal and delaying the data signal by a predetermined time, for output; and

a selection circuit for performing switching control so that when de-emphasis is enabled, a signal obtained on delaying the data signal by said delay circuit is supplied to an input end of said second output buffer; and during the amplitude margin test mode, the data signal is supplied to said input end of said second output buffer;

said first output buffer and said second output buffer being configured to output a signal obtained on subtracting the output of said second buffer from the output of said first buffer, as the output signal.

3. The output buffer according to claim 2 , wherein when de-emphasis is disabled, said second buffer is set in an off state, the amplitude of the output signal is emphasized, for output, at the time of the transition when the logic of the data signal changes, and also at the time of the non-transition when the data signal has the same logic value as that immediately after the transition, the output signal of the same amplitude as the amplitude at the time of the transition is output.

4. An output buffer circuit comprising:

a first output buffer for data, receiving a data signal and outputting an output signal from an output terminal;

a second output buffer having an output end connected to said output terminal;

a delay circuit for receiving the data signal and delaying the data signal by a predetermined time, for output; and

a selection circuit for receiving a control signal indicating whether de-emphasis is enabled or disabled and performing switching control so that when the control signal indicates that the de-emphasis is disabled, said second output buffer is deactivated, when the control signal indicates that the de-emphasis is enabled, emphasis data obtained on delaying the data signal by said delay circuit is supplied to an input end of said second output buffer to cause said second output buffer to operate as a de-emphasis buffer, and

when a test control signal received is of a value indicating an amplitude margin test mode, the data signal is selected to be supplied to the input end of said second output buffer.

5. The output buffer circuit according to claim 4 , wherein

the data signal comprises differential signals;

said first output buffer includes: a first pre-buffer constituted from a differential circuit; and a first main buffer constituted from a differential circuit for receiving a differential output of said first pre-buffer;

said second output buffer includes a second main buffer constituted from a differential circuit;

non-inverting and inverting outputs of the differential output pair of said first main buffer are connected in common with inverting and non-inverting outputs of an differential output pair of said second main buffer, respectively, with common connection nodes thereof being connected to non-inverting and inverting terminals of a differential output terminal pair, respectively; and wherein

said selection circuit receives the differential signal of the data signal and differential signal obtained on delaying the data signal by said delay circuit; and selects and differentially supplies the signal obtained on delaying the data signal by said delay circuit to the input end of said second main buffer when the control signal indicates that the de-emphasis is enabled, while said selection circuit selects and differentially supplies the data signal to said input end of said second output buffer when the test control signal is of a value indicating the amplitude margin test mode.

6. A semiconductor device including said output buffer circuit as set fourth in claim 1 .

7. An interface circuit comprising a transmission system and a reception system; said transmission system including said output buffer circuit as set fourth in claim 1 ;

said interface circuit having an amplitude margin test function of said reception system that receives a signal output from said output buffer circuit.