Semiconductor device
View Patent ↗A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
1. A semiconductor device comprising:
a logic circuit;
a memory cell array including arrayed SRAM cells;
a peripheral circuit for accessing the memory cell array;
a first power supply line of which voltage is a first voltage level;
a second power supply line of which voltage is a second voltage level;
a first MOS transistor; and
a second MOS transistor;
wherein the first voltage level is higher than the second voltage level;
wherein a gate-insulating film thickness of the first MOS transistor is thicker than that of the second MOS transistor;
wherein the first and second power lines supply operating voltage differences to the logic circuit, the memory cell array and the peripheral circuit;
wherein one of the first power supply line and the second power supply line connects to the logic circuit through a source-drain path of the first MOS transistor;
wherein one of the first power supply line and the second power supply line connects to the peripheral circuit through a source-drain path of the second MOS transistor; and
wherein the first and second MOS transistors are nonconductive in a standby state when the logic circuit does not operate.
2. The semiconductor device according to claim 1 ,
wherein the peripheral circuit is a circuit for controlling wordlines of the memory cell array; and
wherein the first power supply connects to the peripheral circuit through a source-drain path of the second MOS transistor.
3. The semiconductor device according to claim 2 ,
wherein the peripheral circuit includes a word driver, a row decoder and a memory controller.
4. The semiconductor device according to claim 1 ,
wherein the peripheral circuit is a circuit for controlling bitlines of the memory cell array; and
wherein the second power supply line connects to the peripheral circuit through a source-drain path of the second MOS transistor.
5. The semiconductor device according to claim 4 ,
wherein the peripheral circuit includes a pre-charge circuit, a read/write amplifier, and a column decoder.
6. The semiconductor device according to claim 1 ,
wherein substrate voltages of MOS transistors of the memory cell array and the peripheral circuit are controlled so as to increase absolute values of threshold voltages in the standby state.
7. A semiconductor device comprising:
a logic circuit;
a memory cell array including arrayed SRAM cells;
a peripheral circuit for accessing the memory cell array;
a first power supply line of which voltage is a first voltage level;
a second power supply of which voltage is a second voltage level;
a first MOS transistor;
a second MOS transistor; and
a third MOS transistor;
wherein the first voltage level is higher than the second voltage level;
wherein a gate-insulating film thickness of the first MOS transistor is thicker than those of the second and third MOS transistors;
wherein the first and second power lines supply an operating voltage difference to the logic circuit;
wherein one of the first power supply line and the second power supply line connects to the logic circuit through a source-drain path of the first MOS transistor;
wherein the first and second power lines connect to the peripheral circuit through source-drain paths of the second and third MOS transistors, respectively;
wherein the first MOS transistor is nonconductive in a standby state when the logic circuit does not operate; and
wherein one of the second MOS transistor and the third MOS transistor is conductive and the other is nonconductive in the standby state.
8. The semiconductor device according to claim 7 ,
wherein the peripheral circuit is a circuit for controlling a wordline of the memory cell array; and
wherein the second MOS transistor is conductive and the third MOS transistor is nonconductive in the standby state.
9. The semiconductor device according to claim 8 ,
wherein the peripheral circuit includes a word driver, a row decoder, and a memory controller.
10. The semiconductor device according to claim 7 ,
wherein the peripheral circuit is a circuit for controlling bitlines of the memory cell array; and
wherein the second MOS transistor is nonconductive and the third MOS transistor is conductive in the standby state.
11. The semiconductor device according to claim 10 ,
wherein the peripheral circuit includes a pre-charge circuit, a read/write amplifier, and a column decoder.
12. The semiconductor device according to claim 7 ,
wherein the peripheral circuit includes a word driver, a row decoder, and a memory controller, a column decoder; and
wherein the second MOS transistor is nonconductive and the third MOS transistor is conductive in the standby state.
13. The semiconductor device to claim 7 ,
wherein substrate voltages of MOS transistors of the memory cell array an the peripheral circuit are controlled so as to increase absolute values of threshold voltages in the standby state.