Semiconducting device having a structure to improve contact processing margin, and method of fabricating the same
View Patent ↗A method for fabricating a semiconductor device includes forming a first insulating pattern, a first conductive pattern, and a second conductive pattern on a semiconductor substrate; forming a spacer on sidewalls of the first insulating pattern, the first conductive pattern, and the second conductive pattern; forming a second insulating pattern over the substrate; forming a first salicide on an exposed portion of the substrate and a second salicide on an entire upper surface of the second conductive pattern; depositing a third insulating layer over the substrate, and etching selectively the third insulating layer to forming first and second contact holes exposing the first and second salicides. The method provides processing margin and prevents excessive etching of a conductive layer under the salicide, even if misalignment of an overlying contact hole happens.
1. Method for fabricating a semiconductor device, comprising the steps of:
(a) forming a first insulating pattern, a first conductive pattern, and a second conductive pattern on a semiconductor substrate;
(b) forming a spacer on sidewalls of the first insulating pattern, the first conductive pattern, and the second conductive pattern;
(c) depositing a second insulating layer over an entire surface of the substrate including the first insulating pattern and the first and second conductive patterns, and forming a second insulating pattern from the second insulating layer exposing an entire upper surface of the second conductive pattern;
(d) forming a first salicide on an exposed substrate and a second salicide on an entire upper surface of the second conductive pattern; and
(e) depositing a third insulating layer over an entire surface of the substrate including the first and second insulating patterns and the first and second conductive patterns, and forming a first contact hole and a second contact hole, respectively exposing the first salicide layer and the second salicide layer, wherein the second contact hole is a predetermined distance from the second insulating pattern and the predetermined distance is more than 60 nm.
2. The method according to claim 1 , wherein the predetermined distance is in the range of 60 nm˜100 nm.
3. The method according to claim 1 , wherein the second insulating layer comprises LP-TEOS or PE-TEOS.
4. The method according to claim 1 , wherein the second insulating layer has a thickness of 600 Ř900 Å.
5. The method according to claim 1 , wherein the first and second salicides comprise Ta silicide, Co silicide, or Ni silicide.
6. The method according to claim 1 , wherein forming the first insulating pattern and the first and second conductive patterns comprises selectively etching a first insulating layer and a conductive layer on the semiconductor substrate.
7. The method according to claim 6 , wherein forming the second insulating pattern comprises dry-etching the second insulating layer using a photoresist pattern as a mask.
8. The method according to claim 7 , further comprising eliminating the photoresist pattern.
9. The method according to claim 8 , wherein forming the first and second contact holes comprises etching selectively the third insulating layer.
10. The method according to claim 1 , further comprising forming first and second contacts in the first and second contact holes, connected to the first salicide layer and the second salicide layer, respectively.
11. A semiconductor device comprising:
(a) a first insulating pattern, a first conductive pattern, and a second conductive pattern on the semiconductor substrate;
(b) a spacer on sidewalls of the first insulating pattern, the first conductive pattern, and the second conductive pattern;
(c) a second insulating pattern on the spacer and the first and second conductive patterns, the second insulating pattern exposing an entire upper surface of the second conductive pattern;
(d) a first salicide on the exposed substrate and a second salicide on an entire upper surface of the second conductive pattern;
(e) a third insulating layer on the second insulating pattern and the first and second salicides; and
(f) first and second contact holes exposing the first salicide and the second salicide, respectively, wherein the second contact hole is a predetermined distance from the second insulating pattern and the predetermined distance is more than 60 nm.
12. The semiconductor device according to claim 11 , wherein the predetermined distance is in the range of 60 nm˜100 nm.
13. The semiconductor device according to claim 11 , wherein the second insulating layer comprises LP-TEOS or PE-TEOS.
14. The semiconductor device according to claim 11 , wherein the second insulating layer has a thickness of 600 Ř900 Å.
15. The semiconductor device according to claim 11 , wherein the first and second salicides comprise Ta silicide, Co silicide, or Ni silicide.
16. The semiconductor device according to claim 11 , further comprising first and second contacts in the first and second contact holes, connected to the first salicide layer and the second salicide layer, receptively.