Semiconductor device and method of manufacturing the same
View Patent ↗The semiconductor device 1 includes an insulating interlayer 10 , interconnects 12 a to 12 c , an insulating interlayer 20 , and a capacitor element 30 . On the insulating interlayer 10 and the interconnects 12 a to 12 d , the insulating interlayer 20 is provided via a diffusion barrier 40 . On the insulating interlayer 20 , the capacitor element 30 is provided. The capacitor element 30 is a MIM type capacitor element, and includes a lower electrode 32 provided on the insulating interlayer 20 , a capacitor insulating layer 34 provided on the lower electrode 32 , and an upper electrode 36 provided on the capacitor insulating layer 34 . The interface S 1 between the insulating interlayer 20 and the capacitor element 30 is generally flat. The lower face S 2 of the insulating interlayer 20 includes an uneven portion at a position corresponding to the capacitor insulating layer 34.
1. A semiconductor device comprising:
a first insulating layer provided on a semiconductor substrate having a first height;
a conductor buried in said first insulating layer having a second height different from said first height;
a second insulating layer provided on said first insulating layer and said conductor, wherein a first surface of said second insulating layer corresponds to said first and second heights and a second surface, opposite said first surface, is generally flat;
a lower electrode provided on said second surface of said second insulating layer;
a capacitor insulating layer provided in a region on said lower electrode opposing at least a part of said conductor; and
an upper electrode provided on said capacitor insulating layer,
wherein said lower electrode is electrically insulated against said conductor under said lower electrode.
2. The semiconductor device according to claim 1 ,
wherein said second height of said conductor is less than said first height of said first insulating layer.
3. The semiconductor device according to claim 1 ,
wherein said second insulating layer is provided on said first insulating layer and said conductor, via a diffusion barrier.
4. The semiconductor device according to claim 1 ,
wherein said conductor is a power interconnect.
5. The semiconductor device according to claim 1 ,
wherein said conductor is a metal predominantly containing copper.