ESD protecting circuit and manufacturing method thereof
View Patent ↗An ESP protecting circuit and a manufacturing method thereof are provided. The ESP protecting circuit includes a device isolation layer, first and second high-concentration impurity regions, a third high-concentration impurity region of a complementary type, first and second conductive wells, and a fourth conductive impurity region. The ESD protecting circuit is configured as a field transistor without a gate electrode, and the high breakdown voltage characteristics of the field transistor are lowered by implanting impurity ions, providing an ESD protecting circuit with a low breakdown voltage and low leakage current. Because the leakage current is reduced, the ESD protecting circuit can be used for an analog I/O device that is sensitive to current fluxes. Also, an N-type well may protect a junction of the field transistor.
1. An ESD (electro-static discharge) protecting circuit comprising:
a device isolation layer in a field region of a semiconductor substrate having a first conductivity type;
first and second high-concentration impurity regions in the semiconductor substrate, isolated from each other by the device isolation layer and having a second conductivity type, wherein the first high-concentration impurity region contacts a first sidewall surface of the device isolation layer and the second high-concentration impurity region contacts a second sidewall surface of the device isolation layer opposite to said first sidewall surface;
a third high-concentration impurity region in the semiconductor substrate, isolated from the second high-concentration impurity region by the device isolation layer, and having the first conductivity type;
a first well in a first portion of the semiconductor substrate in contact with and below the second and third high-concentration impurity regions and below a first portion of the first high-concentration impurity region, and having the first conductivity type
a second well in a second portion of the semiconductor substrate in contact with and below a second portion of the first high-concentration impurity region on one side of the first well, and having the second conductivity type; and
a fourth impurity region below the first high-concentration impurity region at a boundary between the first and second wells, the fourth impurity region separating the first high-concentration impurity region from the first well, and having the first conductivity type.
2. The ESD protecting circuit according to claim 1 , further comprising:
first, second and third silicide layers respectively on surfaces of the first, second and third high-concentration impurity regions;
an insulating layer on the semiconductor substrate;
first, second and third plugs in the insulating layer respectively in contact with the first, second and third silicide layers; and
a plurality of metal lines connected to the first, second and third plugs.
3. The ESD protecting circuit according to claim 1 , wherein the first impurity region has an impurity concentration of 1×10 17 to 1×10 19 atoms/cm 3 .
4. The ESD protecting circuit according to claim 1 , wherein the semiconductor substrate comprises a P-type substrate.
5. The ESD protecting circuit according to claim 1 , wherein the first conductivity type is a P-type.
6. The ESD protecting circuit according to claim 1 , wherein the second conductivity type is an N-type.
7. The ESD protecting circuit according to claim 1 , wherein the first well is a P-type well.
8. The ESD protecting circuit according to claim 1 , wherein the second well is an N-type well.
9. The ESD protecting circuit according to claim 1 , wherein the fourth impurity region is configured to reduce a breakdown voltage of the ESD protecting circuit.
10. The ESD protecting circuit according to claim 2 , wherein the insulating layer is on the first, second and third silicide layers.
11. The ESD protecting circuit according to claim 1 , wherein the fourth impurity region is above a portion of the first well and extends at least from the second well to the device isolation layer between the first and second high-concentration impurity regions.
12. The ESD protecting circuit according to claim 11 , wherein the fourth impurity region is also above a portion of the second well.
13. The ESD protecting circuit according to claim 12 , wherein the fourth impurity region has a width smaller than a width of the first high-concentration impurity region.
14. The ESD protecting circuit according to claim 1 , wherein the fourth impurity region has a width smaller than a width of the first high-concentration impurity region.
15. The ESD protecting circuit according to claim 1 , comprising a bipolar transistor.
16. The ESD protecting circuit according to claim 15 , wherein the third high-concentration impurity region is a base of the bipolar transistor.
17. The ESD protecting circuit according to claim 16 , wherein the first high-concentration impurity region is a collector of the bipolar transistor.
18. The ESD protecting circuit according to claim 17 , wherein the second high-concentration impurity region is an emitter of the bipolar transistor.
19. The ESD protecting circuit according to claim 15 , wherein the fourth impurity region controls breakdown voltage of the bipolar transistor.
20. The ESD protecting circuit according to claim 17 , wherein the fourth impurity region controls breakdown voltage of the bipolar transistor.