Semiconductor device having separated drain regions
View Patent ↗A semiconductor device according to an embodiment of the invention includes: a plurality of field effect transistors; and a plurality of logic circuits composed of the field effect transistors, the field effect transistors each including: first and second drain regions formed away from each other; at least one source region formed between the first and second drain regions; and a plurality of gate electrodes formed between the first drain region and the source region and between the second drain region and the source region.
1. A semiconductor device comprising:
a plurality of field effect transistors; and
a plurality of logic circuits composed of the field effect transistors,
the field effect transistors each comprising:
first and second drain regions formed physically away from each other, wherein the first and second drain regions are electrically connected together to function as one drain region;
at least one source region formed between the first and second drain regions; and
a plurality of gate electrodes formed between the first drain region and the source region and between the second drain region and the source region,
wherein the logic circuits comprise an oscillator circuit in which the plurality of logic circuits are connected in series.
2. The semiconductor device according to claim 1 , wherein the first and second drain regions are interposed between the source regions, or between the source region and a well potential diffusion layer region or a substrate potential diffusion layer region.
3. The semiconductor device according to claim 1 , wherein in the field effect transistor, the number of drain regions formed away from each other is larger than the number of source regions.
4. The semiconductor device according to claim 1 , wherein the plurality of gate electrodes are connected together to function as one gate electrode.
5. The semiconductor device according to claim 1 , wherein a diffusion layer width of each of the drain regions is 0.5 μm or smaller.
6. The semiconductor device according to claim 1 , wherein a power supply voltage of a circuit composed of the field effect transistors is 1.5 V or lower.
7. The semiconductor device according to claim 1 , wherein
said oscillator circuit has a first stage and a second stage,
said oscillator circuit having an isolation region between a first drain region of said first stage and a second drain region of said second stage.
8. A semiconductor device comprising:
a plurality of field effect transistors; and
a plurality of logic circuits composed of the field effect transistors,
the field effect transistors each comprising:
first and second drain regions formed physically away from each other, wherein the first and second drain regions are electrically connected together to function as one drain region;
at least one source region formed between the first and second drain regions; and
a plurality of gate electrodes formed between the first drain region and the source region and between the second drain region and the source region,
wherein the logic circuits comprise a flip-flop circuit.
9. The semiconductor device according to claim 8 , wherein the flip-flop circuit is an SRAM cell.
10. A semiconductor device comprising:
a logic circuit which has two stages; and
one of said stages having two field effect transistors,
each of the two field effect transistors having:
two gate electrodes;
a source region which is formed between the two gate electrodes; and
first and second drain regions provided so that the respective gate electrode is inserted between said source region and the respective drain region, wherein said first and second drain regions of said first stage connects to said gate electrode of said second stage and do not connect to said gate electrode of said first stage.