Method and system for creating and utilizing virtual hardware resources
View Patent ↗A data-processing method and system generally comprises identifying a plurality of hardware resources associated with a data-processing apparatus, time-slicing the plurality of hardware resources. Thereafter the plurality of active hardware resources can be allocated among a plurality of active hardware resources associated with the data-processing apparatus, thereby allowing a limited number of hardware resources to service a larger number of physical devices associated with the data-processing apparatus. An appropriate hardware resource can be selected from among the plurality of active hardware resources utilizing one or more swapping algorithms.
1. A data-processing method comprising:
arranging a plurality of I/O devices in a sequential order;
identifying a plurality of hardware resources associated with a data-processing apparatus;
time-slicing said plurality of hardware resources by executing a program instruction utilizing a computer;
allocating said plurality of active hardware resources among a plurality of active hardware device indices associated with said data-processing apparatus; and
freeing said hardware device indices when said associated active hardware resource is allocated to one of a plurality of drives associated with or in communication with said data-processing apparatus, thereby allowing a limited number of hardware resources to service a larger number of physical devices associated with said data-processing apparatus by executing a program instruction utilizing a computer.
2. The method of claim 1 further comprising selecting an appropriate hardware resource from among said plurality of active hardware resources utilizing at least one swapping algorithm by executing a program instruction utilizing a computer.
3. The method of claim 1 further comprising a pool of free hardware device indices that are available to other data-processing components.
4. The method of claim 3 wherein that at least one free hardware resource among a pool of free hardware resources is allocated and assigned to one of said drives associated with or in communication with said data-processing apparatus.
5. The method of claim 4 wherein a firmware detects at least one input to said drive.
6. The method of claim 1 wherein at least one hardware resource among said plurality of hardware resources comprises a host bus adapter component.
7. The method of claim 6 wherein said host bus adapter component comprises a serial attached SCSI host bus adapter (HBA).
8. A data-processing system comprising:
a data-processing apparatus;
a module executed by said data-processing apparatus, said module and said data-processing apparatus being operable in combination with one another to:
arrange a plurality of I/O devices in a sequential order;
identify a plurality of hardware resources associated with a data-processing apparatus;
time-slice said plurality of hardware resources;
allocate said plurality of active hardware resources among a plurality of active hardware device indices associated with said data-processing apparatus; and
freeing said hardware device indices when said associated active hardware resource is allocated to one of a plurality of drives associated with or in communication with said data-processing apparatus, thereby allowing a limited number of hardware resources to service a larger number of physical devices associated with said data-processing apparatus.
9. The system of claim 8 wherein said data-processing apparatus and said module are further operable in combination with one another to select an appropriate hardware resource from among said plurality of active hardware resources utilizing at least one swapping algorithm.
10. The system of claim 8 further comprising a pool of free hardware device indices that are available to other data-processing components.
11. The system of claim 10 wherein that at least one free hardware resource among a pool of free hardware resources is allocated and assigned one of said drives associated with or in communication with said data-processing apparatus.
12. The system of claim 11 wherein a firmware detects at least one input to said drive.
13. The system of claim 8 wherein at least one hardware resource among said plurality of hardware resources comprises a host bus adapter component.
14. The system of claim 13 wherein said host bus adapter component comprises a serial attached SCSI host bus adapter (HBA).
15. One or more processor readable storage devices having a processor readable code embodied on said processor readable storage devices, said processor readable code for programming one or more processors to perform a method comprising:
arranging a plurality of I/O devices in a sequential order;
identifying a plurality of hardware resources associated with a data-processing apparatus;
time-slicing said plurality of hardware resources;
allocating said plurality of active hardware resources among a plurality of active hardware device indices associated with said data-processing apparatus; and
freeing said hardware device indices when said associated active hardware resource is allocated to one of a plurality of drives associated with or in communication with said data-processing apparatus, thereby allowing a limited number of hardware resources to service a larger number of physical devices associated with said data-processing apparatus.
16. The processor readable code of claim 15 further comprising selecting an appropriate hardware resource from among said plurality of active hardware resources utilizing at least one swapping algorithm.
17. The processor readable code of claim 15 further comprising a pool of free hardware device indices that are available to other data-processing components.
18. The processor readable code of claim 17 wherein that at least one free hardware resource among a pool of free hardware resources is allocated and assigned to one of said drives associated with or in communication with said data-processing apparatus.
19. The processor readable code of claim 18 wherein a firmware detects at least one input to said drive.
20. The processor readable code of claim 15 wherein at least one hardware resource among said plurality of hardware resources comprises a host bus adapter component.