IP Library Granted Patent US 7,379,826
Granted Patent B2
US 7,379,826 · App. 11/504,486 · Granted May 27, 2008

Semiconductor wafer inspection system

Assignee: QCEPT Technologies, Inc.
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Quick Facts
Patent No.
US 7,379,826
App. No.
11/504,486
Granted
May 27, 2008
Kind
B2
Abstract

A method and system for identifying a defect or contamination on a surface of a material. The method and system involves providing a material, such as a semiconductor wafer, using a non-vibrating contact potential difference sensor to scan the wafer, generate contact potential difference data and processing that data to identify a pattern characteristic of the defect or contamination.

Claims (38)

1. A method for identifying a defect present on a surface of a semiconductor wafer being processed for production, comprising the steps of:

providing a semiconductor wafer processing system including a semiconductor wafer scanning system for analyzing defects;

providing a semiconductor wafer having a surface;

fixing the semiconductor wafer upon a wafer stage of the semiconductor wafer scanning system;

providing a contact potential difference sensor;

engaging a positioning mechanism in communication with the contact potential sensor whereby the contact potential difference sensor is positionable in relation to the wafer stage via the positioning mechanism and the contact potential difference sensor is positioned in the in-line semiconductor wafer processing system;

continuously scanning the contact potential difference sensor relative to the wafer;

generating contact potential difference data from the contact potential difference sensor during at least the scanning of the semiconductor wafer relative to the sensor with the data being representative of changes of contact potential difference of the semiconductor wafer surface relative to the contact potential difference sensor;

processing the contact potential difference data to form representative contact potential difference data representative of the semiconductor wafer surface; and

processing the contact potential difference data to identify the defect.

2. The method as defined in claim 1 further including the step of identifying the defect on the wafer disposed on the wafer surface, the defect on the wafer selected from the group consisting of a metal, an organic residue, carbon, an organic compound, an atomic level contaminant and a molecular contaminant.

3. The method as defined in claim 1 further including the step of identifying variations in chemical oxide state of an oxide material disposed on at least part of the wafer.

4. The method as defined in claim 3 wherein the oxide material comprises a silicon based material.

5. The method as defined in claim 1 wherein the surface of the semiconductor wafer being inspected comprises at least one of a front side of the wafer, a back side of the wafer and an edge of the wafer.

6. The method as defined in claim 1 wherein the defect on the semiconductor wafer comprises a geometrical change in the wafer surface.

7. The method as defined in claim 6 wherein the geometrical change is selected from the group of a surface scratch, a surface crack, an etched trench, a pinhole, a particle, a bubble, and a delaminated portion of the wafer.

8. The method as defined in claim 1 wherein the defect comprises defects which give rise to electrostatic fields.

9. The method as defined in claim 1 wherein the defect comprises at least one of a thin dielectric film disposed on the wafer and a nonconducting material disposed on the wafer.

10. The method as defined in claim 1 wherein the defect comprises at least one of defect states, chemical states, electrostatic states and mechanical features.

11. The method as defined in claim 1 wherein the defect comprises a feature associated with a change of relative contact potential difference over the surface of the wafer.

12. The method as defined in claim 1 further including another inspection system for evaluating properties of the semiconductor wafer.

13. In a method for identifying a defect present on a surface of a semiconductor wafer being processed for production, the semiconductor wafer having undergone at least one preprocessing step of: applying processing chemicals, subjecting the semiconductor wafer to another processing step, cleaning the semiconductor wafer, and handling the semiconductor wafer, the improvement comprising the steps of:

providing a semiconductor wafer processing system including a semiconductor wafer scanning system for analyzing defects of the semiconductor wafer;

providing a semiconductor wafer having a surface, the semiconductor wafer having undergone the at least one preprocessing step;

fixing the semiconductor wafer upon a wafer stage of the semiconductor wafer scanning system;

providing a contact potential difference sensor;

engaging a positioning mechanism in communication with the contact potential sensor whereby the contact potential difference sensor is positionable in relation to the wafer stage via the positioning mechanism and the contact potential difference sensor is positioned in the in-line semiconductor wafer processing system;

continuously scanning the contact potential difference sensor relative to the wafer;

generating contact potential difference data from the contact potential difference sensor during at least the scanning of the semiconductor wafer relative to the sensor with the data being representative of changes of contact potential difference of the semiconductor wafer surface relative to the contact potential difference sensor;

processing the contact potential difference data to form representative contact potential difference data representative of the semiconductor wafer surface; and

processing the contact potential difference data to identify the defect.

14. The improvement of claim 13 wherein the processing of the contact potential difference data comprises sensing a variation in an insulating layer disposed on at least part of the semiconductor wafer.

15. The improvement of claim 14 wherein the defect includes an anomalous electrostatic field.

16. The improvement of claim 14 wherein the insulating material consists essentially of a silicon oxide.

17. The improvement of claim 13 the defect comprises at least one of a residue, a chemical contaminant, a metal, carbon, an organic compound, an atomic level contaminant and a molecular contaminant arising from the one preprocessing step of the semiconductor wafer.

18. The improvement of claim 13 further including the step of classifying the defect in terms of the change of the relative contact potential difference over the surface of the semiconductor wafer.

19. The improvement of claim 13 wherein the defect is selected from the group of a chemical defect, an electrical defect and a geometrical change.

20. The improvement of claim 13 wherein the step of generating contact potential difference data includes collecting data from a semiconductor wafer surface selected from the group consisting of a front side of the wafer, a back side of the wafer and an edge of the wafer.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Aug 3, 2016
From: PNC BANK NATIONAL ASSOCIATION SUCCESSOR TO RBC BANK (USA)
To: QCEPT TECHNOLOGIES INC
Reel/Frame 039331/0211 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2016
From: QCEPT TECHNOLOGIES INC.
To: QCEPT INVESTMENTS LLC
Reel/Frame 039151/0780 →
SECURITY AGREEMENT Recorded Feb 6, 2014
From: PNC BANK FORMERLY RBC BANK
To: QCEPT TECHNOLOGIES INC.
Reel/Frame 032164/0589 →
SECURITY AGREEMENT Recorded Mar 23, 2012
From: QCEPT TECHNOLOGIES INC.
To: RBC BANK (USA)
Reel/Frame 027919/0635 →
Continuity (4)
Continuation 1115608800 · Jun 17, 2005
Continuation 1063146900 · Jul 29, 2003
Provisional Application 6044450400 · Feb 3, 2003
Related Publication 20060276976A1 · Dec 7, 2006