IP Library Granted Patent US 7,425,494
Granted Patent B2
US 7,425,494 · App. 11/504,560 · Granted Sep 16, 2008

Method for forming void-free trench isolation layer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,425,494
App. No.
11/504,560
Granted
Sep 16, 2008
Kind
B2
Abstract

Disclosed method for forming void-free isolation comprises the steps of: forming a trench in an isolation region in a semiconductor substrate; and forming a filling oxide on the semiconductor substrate to fill the trench. The filling oxide is formed by HDP-CVD process and by using reactant gas mixture that includes O 2 , SiH 4 and He. In an embodiment of the present invention, the formation of the filling oxide is carried out in two-step process which includes: first filling the trench with the filling oxide under the first processing condition that a first D/S value has a greater deposition rate than sputter etching rate; and second filling the trench with the filling oxide under the second processing condition that a second D/S value is smaller than the first D/S value. Here the D/S value is defined as “(net deposition rate+blanket sputter etching rate)/(blanket sputter etching rate)”.

Claims (25)

1. A method for forming a trench isolation comprising the steps of:

forming a trench in an isolation region in a semiconductor substrate; and

filling the trench with an oxide by high density plasma chemical vapor deposition (HDP-CVD) using a reactant gas mixture that includes O 2 , SiH 4 and He, wherein filling the trench includes depositing the oxide under first conditions such that a first D/S value has a greater deposition rate than a corresponding sputter etching rate; and

depositing the oxide under second conditions such that a second D/S value is smaller than the first D/S value, wherein the D/S value is defined as (net deposition rate+blanket sputter etching rate)/(blanket sputter etching rate).

2. The method as claimed in claim 1 , wherein the CVD deposition rate of the first and second conditions is controlled by the flow rate of SiH 4 and the rate of sputter etching is controlled by a bias power.

3. The method as claimed in claim 1 , wherein the first D/S value is equal to or greater than 33.6.

4. The method as claimed in claim 1 , further comprising, before the step of filling the trench with oxide, forming a silicon nitride in the trench and on the overall surface of the semiconductor substrate.

5. The method as claimed in claim 4 , wherein forming the silicon nitride comprises low pressure chemical vapor deposition (LPCVD).

6. The method as claimed in claim 4 , wherein the silicon nitride has a thickness of 20 nm.

7. The method as claimed in claim 5 , wherein the silicon nitride has a thickness of 20 nm.

8. The method as claim in claim 1 , wherein forming the oxide comprises introducing SiH 4 at a flow rate of approximately 50-90 sccm into a deposition chamber.

9. The method as claimed in claim 8 , wherein the conditions further comprise introducing at flow rates of about 100-120 sccm of O 2 and about 50-150 sccm of He.

10. The method as claim in claim 1 , wherein the oxide is formed under conditions comprising a flow rate of SiH 4 introduced to a side of a chamber of approximately 59 sccm, and a flow rate of SiH 4 introduced into a top of the chamber of approximately 8.1 sccm.

11. The method as claimed in claim 10 , wherein the conditions further comprise flow rates of O 2 and He introduced to the side of the chamber of about 109 sccm of O 2 and about 100 sccm of He.

12. The method as claimed in claim 1 , wherein the oxide is formed in a reaction chamber at a vacuum pressure of 3 mTorr and a semiconductor substrate temperature of 700° C.

13. The method as claimed in claim 12 , wherein the oxide is formed at a bias power of from 1935 W to 2365 W.

14. The method as claimed in claim 1 , wherein forming the oxide comprises depositing the oxide in a reaction chamber at a pressure of 0.5-10 mTorr.

15. The method as claimed in claim 14 , wherein the oxide is deposited at a substrate temperature of 600-900° C.

16. The method as claimed in claim 15 , wherein the oxide is deposited at a bias power of from 1800 W to 2500 W.

17. A method for forming a trench isolation comprising steps of:

forming a trench in an isolation region in a semiconductor substrate;

filling the trench with an oxide by high density plasma chemical vapor deposition (HDP-CVD) using a reactant gas mixture that includes O 2 , SiH 4 and He, wherein filling the trench includes depositing a first part of the oxide at a first D/S value of greater than 10; and

depositing a second part of the oxide at a second D/S value of 10 or less, wherein the D/S value equals (net deposition rate+sputter etching rate)/(sputter etching rate).

18. The method as claimed in claim 17 , wherein the first D/S value is at least 28, and the second D/S value is less than 10.

19. The method as claimed in claim 17 , wherein the first part of the oxide does not fill the trench, and the second part of the oxide is deposited in an amount sufficient to fill the trench.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041426/0957 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2006
From: PARK, KYUNG MIN
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018203/0211 →