A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
1. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said memory chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memory chips, and converting memory output signals output from said memory chips into controller input signals receivable to said controller; and
a common bus for connecting said chips and said memory controller to transmit said memory input signals and said memory output signals, wherein the common bus includes a command signal line and a data signal line,
wherein said memory input signals include at least two differing memory input signals, each of with corresponds to a different one of the plurality of different types of memories.
2. The memory system according to claim 1 , further comprising an address line between the memory controller and one of the plurality of different types of memories.
3. The memory system according to claim 1 , wherein said memory output signals include at least two differing memory output signals, each of which corresponds to a different one of the plurality of different types of memories.
4. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said memory chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller;
at least one command lines being shared with the plurality of different types of memories; and
at least one data lines shared with the plurality of different types of memories, wherein the at least one command lines and the at least one data lines form a common bus,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
5. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories, the plurality of chips operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller; and
a common bus for connecting said chips and said memory controller to transmit said memory input signals and said memory output signals, wherein the common bus includes a command signal line and a data signal line,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
6. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories, the plurality of chips operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller;
at least one command lines being shared with the plurality of different types of memories; and
at least one data lines shared with the plurality of different types of memories, wherein the at least one command lines and the at least one data lines form a common bus,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
7. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller; and
a common bus for connecting said memories and said memory controller to transmit said memory input signals and said memory output signals, wherein the common bus includes only a address signal line and a data signal line,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
8. The memory system according to claim 7 , further comprising a command line provided to each of the plurality of different types of memories.
9. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller;
a plurality of command lines being provided for each of the plurality of different types of memories; and
a common bus for connecting said memories and said memory controller to transmit said memory input signals and said memory output signals, wherein the common bus includes a address signal line and a data signal line,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
10. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller;
at least one individual command line connected between the memory controller and one of the plurality of different types of memories;
at least one address lines being shared with the plurality of different types of memories; and at least one data lines shared with the plurality of different types of memories, wherein the at least one address lines and the at least one data lines form a common bus,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
11. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories, the plurality of chips operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller; and
a common bus for connecting said memories and said memory controller to transmit said memory input signals and said memory output signals, wherein the common bus includes only a address signal line and a data signal line,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
12. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories, the plurality of chips operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller;
a plurality of command lines being provided for each of the plurality of different types of memories; and
a common bus for connecting said memories and said memory controller to transmit said memory input signals and said memory output signals, wherein the common bus includes a address signal line and a data signal line,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
13. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories, the plurality of chips operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller;
at least one individual command line connected between the memory controller and one of the plurality of different types of memories;
at least one address lines being shared with the plurality of different types of memories; and at least one data lines shared with the plurality of different types of memories, wherein the at least one address lines and the at least one data lines form a common bus,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
14. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller; and
a common bus for connecting said memories and said memory controller to transmit said memory input signals and said memory output signals, wherein the common bus includes only at least one data signal line,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
15. The memory system according to claim 14 , further comprising a command line provided to each of the plurality of different types of memories.
16. The memory system according to claim 14 , further comprising an address line provided to one of the plurality of different types of memories.
17. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories operating in with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller;
a plurality of command lines provided for each of the plurality of different types of memories; and
a common bus for connecting said memories and said memory controller to transmit said memory input signals and said memory output signals, wherein the common bus includes at least one data signal line,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
18. The memory system according to claim 17 , further comprising an address line provided to one of the plurality of different types of memories.
19. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories, the plurality of chips operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
a memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller; and
a common bus for connecting said memories and said memory controller to transmit said memory input signals and said memory output signals, wherein the common bus includes only at least one data signal line,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.
20. A memory system comprising:
a plurality of chips including a respective memory among a plurality of different types of memories, the plurality of chips operating with different specifications and in synchronization with a clock signal;
a controller for outputting controller output signals to access said chips;
memory controller for converting said controller output signals into memory input signals according to operation specifications of said respective memories, and converting memory output signals output from said memories into controller input signals receivable to said controller;
a plurality of command lines provided for each of the plurality of different types of memories; and
a common bus for connecting said memories and said memory controller to transmit said memory input signals and said memory output signals, wherein the common bus includes at least one data signal line,
wherein said memory input signals include at least two differing memory input signals, each of which corresponds to a different one of the plurality of different types of memories.