Delta-sigma modulator circuits in which DITHER is added to the quantization levels of methods of operating the same

1. A delta-sigma modulator circuit, comprising:

an n-level quantizer circuit that is configured to generate a quantized output signal responsive to an input signal, the n-level quantizer circuit comprising:

n adder circuits that are configured to add a dither signal to n quantization levels to generate n dithered quantization levels, respectively; and

n comparator circuits that are configured to compare the input signal with the n dithered quantization levels to generate the quantized output signal;

a dither generator that is configured to generate the dither signal; and

a scaling circuit that is configured to multiply the dither signal by a scaling factor to generate the scaled dither signal;

wherein the n adder circuits are configured to add the scaled dither signal to the n quantization levels to generate the n dither quantization levels, respectively.

2. The delta-sigma modulator circuit of claim 1 , further comprising:

an integrator that is configured to integrate a difference between a modulator input signal and the quantized output signal to generate the input signal.

3. The delta-sigma modulator circuit of claim 2 , wherein the integrator comprises a loop filter.

4. The delta-sigma modulator circuit of claim 2 , further comprising:

an interpolator circuit that is configured to generate the modulator input signal responsive to a digital input signal.

5. The delta-sigma modulator circuit of claim 4 , wherein the interpolator circuit comprises a digital low pass filter.

6. The delta-sigma modulator circuit of claim 1 , further comprising:

a digital-to-analog converter (DAC) circuit that is configured to generate an analog output signal responsive to the quantized output signal.

7. The delta-sigma modulator circuit of claim 1 , further comprising:

a scaler block that is configured to generate the scaling factor based on a scale control signal.

8. The delta-sigma modulator circuit of claim 1 , wherein the scaling circuit comprises:

n scaling units that are associated with the n adder circuits, respectively, the n scaling units being configured to multiply the dither signal by n scaling factors to generate n scaled dither signals;

wherein the n adder circuits are further configured to add the n scaled dither signals to the n quantization levels to generate the n dithered quantization levels.

9. The delta-sigma modulator circuit of claim 8 , wherein the n scaling factors have different values.

10. The delta-sigma modulator circuit of claim 8 , wherein at least two of the n scaling factors have a same value.

11. The delta sigma modulator circuit of claim 8 , wherein scaling factors associated with quantization levels between a first threshold and a second threshold are greater than scaling factors associated with quantization levels less than the first threshold and greater than the second threshold.

12. The delta-sigma modulator circuit of claim 1 , wherein the dither signal comprises non-periodic pseudo random noise.

13. The delta-sigma modulator circuit of claim 1 , further comprising:

a digital-to-analog converter (DAC) that is configured to generate an analog output signal responsive to the quantized output signal; and

an integrator that is configured to integrate a difference between a modulator input signal and the analog output signal to generate the input signal.

14. The delta-sigma modulator circuit of claim 13 , wherein the integrator comprises a loop filter.

15. The delta-sigma modulator circuit of claim 13 , further comprising:

an analog low pass filter that is configured to generate the modulator input signal responsive to an analog input signal.

16. The delta-sigma modulator circuit of claim 1 , further comprising:

a decimator circuit that is configured to generate a digital output signal responsive to the quantized output signal.

17. The delta-sigma modulator circuit of claim 16 , wherein the decimator circuit comprises a digital low pass filter.

18. A method of operating a delta-sigma modulator, comprising:

generating a dither signal;

multiplying the dither signal by a scaling factor to generate a scaled dither signal;

generating a quantized output signal responsive to an input signal, comprising:

adding the scaled dither signal to n quantization levels to generate n dithered quantization levels, respectively; and

comparing the input signal with the n dithered quantization levels to generate the quantized output signal.

19. The method of claim 18 , further comprising:

integrating a difference between a modulator input signal and the quantized output signal to generate the input signal.

20. The method of claim 18 , further comprising:

interpolating a digital input signal to generate the modulator input signal.

21. The method of claim 18 , further comprising:

converting the quantized output signal to an analog output signal.

22. The method of claim 18 , further comprising:

generating the scaling factor based on a scale control signal.

23. The method of claim 18 , wherein multiplying the dither signal by the scaling factor comprises:

multiplying the dither signal by n scaling factors to generate n scaled dither signals;

wherein adding the scaled dither signal to the n quantization levels comprises:

adding the n scaled dither signals to the n quantization levels to generate the n dithered quantization levels.

24. The method of claim 23 , wherein the n scaling factors have different values.

25. The method of claim 23 , wherein at least two of the n scaling factors have a same value.

26. The method of claim 23 , wherein scaling factors associated with quantization levels between a first threshold and a second threshold are greater than scaling factors associated with quantization levels less than the first threshold and greater than the second threshold.

27. The method of claim 18 , wherein the dither signal comprises non-periodic pseudo random noise.

28. The method of claim 18 , further comprising:

converting the quantized output signal to an analog output signal; and

integrating a difference between a modulator input signal and the analog output signal to generate the input signal.

29. The method of claim 28 , further comprising:

low pass filtering an analog input signal to generate the modulator input signal.

30. The method of claim 18 , further comprising:

generating a digital output signal responsive to the quantized output signal.