IP Library Granted Patent US 7,504,812
Granted Patent B2
US 7,504,812 · App. 11/506,957 · Granted Mar 17, 2009

Transient behavior while switching between control loops in a switching voltage regulator

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Quick Facts
Patent No.
US 7,504,812
App. No.
11/506,957
Granted
Mar 17, 2009
Kind
B2
Abstract

A voltage switching regulator includes a pulsewidth modulation (PWM) controller providing voltage regulation when the voltage switching regulator is experiencing being in an high-power mode. A pulse-frequency modulation (PFM) controller provides voltage regulation when the voltage switching regulator is experiencing being in a low-power mode. An error-voltage estimator enables switching between the low-power mode and the high-power mode while keeping the voltage switching regulator output in regulation between the desired minimum and maximum voltages.

Claims (22)

1. A voltage switching regulator comprising:

a pulsewidth modulation (PWM) controller for providing voltage regulation when said voltage switching regulator is experiencing being in a high-power mode;

a pulse-frequency modulation (PFM) controller for providing voltage regulation when said voltage switching regulator is experiencing being in a low-power mode; and

an error-voltage estimator for enabling switching between the low-power mode and the high-power mode while keeping the voltage switching regulator output in regulation between the desired minimum and maximum voltages, said error voltage estimator is active during said high-power mode and estimates an equilibrium voltage at the output of an error amplifier that is required during said low-power mode, the equilibrium voltage is applied as an initial condition at the output of said error amplifier when transitioning from the high-power mode to the low-power mode, wherein the transient disturbance during changeover is completely suppressed.

2. The voltage switching regulator of claim 1 , wherein said error estimator is incorporated with said PWM controller.

3. The voltage switching regulator of claim 1 , wherein said PFM controller uses less then 10 μA for power consumption.

4. The voltage switching regulator of claim 1 , wherein said PWM controller comprises a high-gain error amplifier.

5. The voltage switching regulator of claim 4 , wherein said high-gain error amplifier is coupled to said error-voltage estimator via an inverter circuit.

6. The voltage switching regulator of claim 5 , wherein said error-voltage estimator drives said inverter circuit to produce an estimated equilibrium error voltage.

7. The voltage switching regulator of claim 6 , wherein said estimated equilibrium error voltage is stored in a capacitor associated with said inverter circuit.

8. The voltage switching regulator of claim 6 , wherein said error-voltage estimator uses said estimated equilibrium error voltage to transition between said low-power mode and said high-power mode.

9. A method for performing voltage switching regulation comprising:

providing a pulsewidth modulation (PWM) controller for providing voltage regulation when a voltage switching regulator is experiencing being in a high-power mode;

providing a pulse-frequency modulation (PFM) controller for providing voltage regulation when said voltage switching regulator is experiencing being in a low-power mode; and

providing an error-voltage estimator for enabling switching between the low-power mode and the high-power mode while keeping the voltage switching regulator output in regulation between the desired minimum and maximum voltages, said error voltage estimator is active during said high-power mode and estimates an equilibrium voltage at the output of an error amplifier that is required during said low-power mode, the equilibrium voltage is applied as an initial condition at the output of said error amplifier when transitioning from the high-power mode to the low-power mode, wherein the transient disturbance during changeover is completely suppressed.

10. The method of claim 9 , wherein said error-voltage estimator is incorporated with said PWM controller.

11. The method of claim 9 , wherein said PFM controller uses less then 10 μA for power consumption.

12. The method of claim 9 , wherein said PWM controller comprises a high-gain error amplifier.

13. The method of claim 12 , wherein said high-gain error amplifier is coupled to said error-voltage estimator via an inverter circuit.

14. The method of claim 13 , wherein said error-voltage estimator drives said inverter circuit to produce an estimated equilibrium error voltage.

15. The method of claim 14 , wherein said estimated equilibrium error voltage is stored in a capacitor associated with said inverter circuit.

16. The method of claim 14 , wherein said error-voltage estimator uses said estimated equilibrium error voltage to transition between said low-power mode and high-power mode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2008
From: ANALOG DEVICES, INC.
To: MEDIATEK, INC.
Reel/Frame 020550/0993 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2006
From: RIEHL, PATRICK S.
To: ANALOG DEVICES, INC.
Reel/Frame 018349/0222 →