Differential output circuit with stable duty

1. A differential output circuit, comprising:

a bias circuit connected with a first voltage;

an input circuit section comprising first and second MOS transistors of a first conductive type, wherein said first and second MOS transistors are connected with said first voltage through said bias circuit, and gates of said first and second MOS transistors receive a differential input signal;

first and second resistance elements; and

third and fourth MOS transistors of a second conductive type connected with said first and second MOS transistors through said first and second resistance elements, respectively, and connected with a second voltage,

wherein a first connection node between said first MOS transistor and said first resistance element is connected with a gate of said fourth MOS transistor,

wherein a second connection node between said second MOS transistor and said second resistance element is connected with a gate of said third MOS transistor,

wherein a differential output signal is outputted from a first output node between said first resistance element and said third MOS transistor and a second output node between said second resistance element and said fourth MOS transistor in response to said differential input signal and

wherein said bias circuit comprises:

a third resistance element connected between said first MOS transistor and the first voltage;

a fourth resistance element connected between said second MOS transistor and the first voltage; and

a capacitance element connected between a first node between said first MOS transistor and said third resistance element and a second node between said second MOS transistor and said fourth resistance element.

2. The differential output circuit according to claim 1 , wherein said third and fourth resistance elements are constituted by fifth and sixth MOS transistors of the first conductive type which have gates connected with the second voltage, respectively.

3. The differential output circuit according to claim 1 , wherein said capacitance element is constituted by a first additional MOS transistor having a source and a drain connected to said first node and a gate connected to said second node and a second additional MOS transistor having a source and a drain connected to said second node and a gate connected to said first node.

4. A differential output circuit, comprising:

a bias circuit connected with a first voltage;

an input circuit section comprising first and second MOS transistors of a first conductive type, wherein said first and second MOS transistors are connected with said first voltage through said bias circuit, and gates of said first and second MOS transistors receive a differential input signal;

first and second resistance elements;

third and fourth MOS transistors of a second conductive type connected with said first and second MOS transistors through said first and second resistance elements, respectively, and connected with a second voltage; and

fifth and sixth MOS transistors of the first conductive type which have gates connected with a second differential input signal,

wherein a first connection node between said first MOS transistor and said first resistance element is connected with a gate of said fourth MOS transistor,

wherein a second connection node between said second MOS transistor and said second resistance element is connected with a gate of said third MOS transistor, and

wherein a differential output signal is outputted from a first output node between said first resistance element and said third MOS transistor and a second output node between said second resistance element and said fourth MOS transistor in response to said differential input signal.

5. The differential output circuit according to claim 4 , wherein said fifth and sixth MOS transistors are respectively provided in series to said first and second MOS transistors.

6. The differential output circuit according to claim 4 , wherein said fifth and sixth MOS transistors are respectively provided in parallel to said first and second MOS transistors.

7. The differential output circuit according to claim 4 , wherein said first and second resistance elements are constituted by seventh and eighth MOS transistors of the first conductive type which have gates connected with the second voltage, respectively.

8. The differential output circuit according to claim 4 , wherein said bias circuit comprises:

a third resistance element connected between said first MOS transistor and the first voltage;

a fourth resistance element connected between said second MOS transistor and the first voltage; and

a capacitance element connected between said first MOS transistor and the first voltage and between said second MOS transistor and the first voltage.

9. The differential output circuit according to claim 8 , wherein said third and fourth resistance elements are constituted by ninth and tenth MOS transistors of the first conductive type which have gates connected with the second voltage, respectively.

10. The differential output circuit according to claim 4 , further comprising a fifth resistance element between said first and second output nodes.

11. The differential output circuit according to claim 10 , wherein said fifth resistance element is constituted by an eleventh MOS transistor of the first conductive type which has a gate connected with a predetermined voltage.