Semiconductor device
View Patent ↗A semiconductor device according to an embodiment of the present invention includes: an oscillating circuit including a plurality of logic circuits connected in series; and an error detecting circuit receiving output signals of at least two of the plurality of logic circuits, and suspending an operation of the oscillating circuit to notify other blocks of the oscillating circuit that an error occurs in the oscillating circuit if a phase difference between the output signals is not within a predetermined phase difference range.
1. A semiconductor device, comprising:
a ring oscillating circuit including 2n+1 logic circuits connected in series, where n is an integer of 1 or greater; and
an error detecting circuit receiving output signals of at least two of the logic circuits and outputting an error detection signal if a phase difference between the output signals is not within a predetermined phase difference range, the error detecting circuit including a monitor circuit which outputs to a determination circuit, and the determination circuit outputs to a control circuit, the monitor circuit including a plurality of phase comparators,
wherein the at least 2n+1 logic circuits includes at least one of a second to a 2n logic circuit that are connected by the error detecting circuit to a last logic gate of the 2n+1 logic circuits so that each of the plurality of the phase comparators is configured to receive output waveforms of two inverter circuits of the 2n+1 logic circuits such that the determination circuit determines that if a phase difference between output waveforms of the two inverter circuits is within a predetermined range a Low level signal is output to the control circuit or otherwise a High level signal is output to the control circuit, and the control circuit outputs an output of the last circuit of the ring oscillator circuit to OUT if the signal is LOW.
2. The semiconductor device according to claim 1 , wherein the error detecting circuit includes:
the determination circuit determining whether or not the oscillating circuit normally operates based on the detection signal; and
the control circuit outputting the error detection signal based on a determination result of the determination circuit.
3. The semiconductor device according to claim 1 , wherein the monitor circuit monitors an output of at least a (2n+1)/k-th circuit of the logic circuits, and k is smaller than n and is a submultiple of 2n+1.
4. The semiconductor device according to claim 2 , wherein the monitor circuit monitors an output of at least a (2n+1)/k-th circuit of the logic circuits, and k is smaller than n and is a submultiple of 2n+1.
5. The semiconductor device according to claim 1 , wherein the control circuit has a function of sending an output signal of the oscillating circuit after an elapse of a predetermined period from power-on.
6. The semiconductor device according to claim 2 , wherein the error detection signal suspends an operation of the oscillating circuit and notifies other blocks that an error occurs in the oscillating circuit.
7. The semiconductor device according to claim 1 , wherein the error detection signal suspends an operation of the oscillating circuit and notifies other blocks that an error occurs in the oscillating circuit.
8. The semiconductor device according to claim 1 , wherein an output terminal of the logic gate is series connected with the logic circuits.
9. The semiconductor device according to claim 2 , wherein the output signals are taken from nodes that are adjacent to at least two of the logic circuits therebetween.
10. The semiconductor device according to claim 2 , wherein the output signals are taken from three connecting points of the logic circuits.
11. A semiconductor device, comprising:
a ring oscillating circuit including 2n+1 logic circuits connected in series, where n is an integer of 1 or greater, the plurality of logic circuits being a logic gate having an output terminal series connected to a plurality of inverter circuits, and an output terminal of a last inverter circuit is connected to an input terminal of the logic gate; and
an error detecting circuit receiving output signals of at least two of the logic circuits and outputting an error detection signal if a phase difference between the output signals is not within a predetermined phase difference range, the error detecting circuit including a monitor circuit which outputs to a determination circuit, and the determination circuit outputs to a control circuit, the monitor circuit including a plurality of phase comparators,
wherein the at least 2n+1 logic circuits includes at least one of a second to a 2n logic circuit that are connected by the error detecting circuit to the logic gate of the 2n+1 logic circuits so that each of the plurality of the phase comparators is configured to receive output waveforms of two inverter circuits of the 2n+1 logic circuits such that the determination circuit determines that if a phase difference between output waveforms of the two inverter circuits is within a predetermined range a Low level signal is output to the control circuit or otherwise a High level signal is output to the control circuit, and the control circuit outputs an output of the last circuit of the ring oscillator circuit to OUT if the signal is LOW.
12. The semiconductor device according to claim 11 , wherein the error detecting circuit includes:
the determination circuit determining whether or not the oscillating circuit normally operates based on the detection signal; and
the control circuit outputting the error detection signal based on a determination result of the determination circuit.
13. The semiconductor device according to claim 12 , wherein the monitor circuit monitors an output of at least a (2n+1)/k-th circuit of the logic circuits, and k is smaller than n and is a submultiple of 2n+1.
14. A semiconductor device, comprising:
a ring oscillating circuit including 2n+1 logic circuits connected in series, where n is an integer of 1 or greater; and
a soft error detecting circuit receiving output signals of at least two of the logic circuits and outputting an error detection signal if a phase difference between the output signals is not within a predetermined phase difference range, the soft error detecting circuit including a monitor circuit which outputs to a determination circuit, and the determination circuit outputs to a control circuit, the monitor circuit including a plurality of phase comparators,
wherein the at least 2n+1 logic circuits includes at least one of a second to a 2n logic circuit that are connected by the error detecting circuit to a last logic gate of the 2n+1 logic circuits so that each of the plurality of the phase comparators is configured to receive output waveforms of two inverter circuits of the 2n+1 logic circuits such that the determination circuit determines that if a phase difference between output waveforms of the two inverter circuits is within a predetermined range a Low level signal is output to the control circuit or otherwise a High level signal is output to the control circuit, and the control circuit outputs an output of the last circuit of the ring oscillator circuit to OUT if the signal is LOW,
wherein the soft error detecting circuit is configured to detect soft errors caused by radiation.
15. The semiconductor device according to claim 14 , wherein the semiconductor device is configured to supply a reset signal to an internal circuit of the ring oscillator circuit and the logic gate of the ring oscillator circuit, such that when soft errors occur, operation of the ring oscillator circuit and notify an internal circuit of the soft errors is suspended.
16. The semiconductor device according to claim 15 , wherein the semiconductor device is configured so that a processing executed before the soft error occurs or reread data based on the reset signal is resumed by the internal circuit, whereby the soft error is prevented from propagating.