IP Library Granted Patent US 7,948,056
Granted Patent B2
US 7,948,056 · App. 11/509,577 · Granted May 24, 2011

Integrated electronic device and method of making the same

Assignees: Fujitsu Limited; Taiyo Yuden Co., Ltd.
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Quick Facts
Patent No.
US 7,948,056
App. No.
11/509,577
Granted
May 24, 2011
Kind
B2
Abstract

An integrated electronic device includes a substrate, passive components, pads for external connection, and three-dimensional wiring. The passive components includes a multi-stage coil inductor provided on the substrate. The multi-stage coil inductor has a plurality of coils disposed in several layers. Mutually adjacent coil wires are spaced-apart from each other. The three-dimensional wiring includes a first wiring portion which extends on the substrate, a second wiring portion which extends off the substrate but along the substrate, and a third wiring portion connecting with the first wiring portion and the second wiring portion.

Claims (20)

1. An integrated electronic device including:

a substrate;

a plurality of passive components;

a plurality of pads for external connection; and

three-dimensional wiring;

wherein the plurality of passive components include a multi-layer coil inductor provided on the substrate, the multi-layer coil inductor including a plurality of coils disposed in a plurality of layers and spaced apart from each other by a gap in a direction in which the layers are stacked,

wherein each of the plurality of coils is exposed to space.

2. The integrated electronic device according to claim 1 , wherein each of the coils is a spiral coil.

3. The integrated electronic device according to claim 2 , wherein the coils are connected in series to each other, and directions of electric currents passing through the coils are same.

4. The integrated electronic device according to claim 1 , wherein the substrate is one of a semiconductor substrate, a semiconductor substrate having a surface formed with an insulation film, a quartz substrate, a glass substrate, a piezoelectric substrate, a ceramic substrate, an SOI substrate, an SOQ substrate and an SOG substrate.

5. The integrated electronic device according to claim 1 , wherein the plurality of passive components include a capacitor and/or a resistor.

6. The integrated electronic device according to claim 5 , wherein the capacitor includes a first and a second electrodes opposed to each other, the first electrode being provided on the substrate, the second electrode being provided off and along the substrate.

7. The integrated electronic device according to claim 1 , wherein the multi-stage coil inductor includes a coil closest to the substrate, the closest coil being spaced apart from the substrate.

8. The integrated electronic device according to claim 1 , wherein the multi-layer coil inductor includes a coil closest to the substrate, the closest coil being formed as a pattern on the substrate.

9. The integrated electronic device according to claim 1 , wherein the plurality of passive components include one of an LCR filter, an SAW filter, an FBAR filter and a mechanical oscillation filter.

10. The integrated electronic device according to claim 1 , further comprising a resin sealant for sealing the passive components and the three-dimensional wiring on the substrate.

11. The integrated electronic device according to claim 10 , wherein the resin sealant has a portion entering between the coils in the multi-layer coil inductor.

12. The integrated electronic device according to claim 1 , wherein the multi-layer coil inductor and/or the three-dimensional wiring has a portion coated with one of a corrosion-resistant film, a magnetic film and a multi-layered film that includes the corrosion-resistant film or the magnetic film.

13. The integrated electronic device according to claim 1 , wherein the substrate has a recess, the multi-stage coil inductor being provided in the recess.

14. The integrated electronic device according to claim 1 , wherein the three-dimensional wiring includes a first wiring portion extending on the substrate, a second wiring portion spaced away from and extending along the substrate, and a third wiring portion connecting the first and the second wiring portions.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2020
From: FUJITSU LIMITED
To: TAIYO YUDEN CO., LTD.
Reel/Frame 051481/0463 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2011
From: TAKAHASHI, TAKEO
To: FUJITSU LIMITED; TAIYO YUDEN CO., LTD.
Reel/Frame 025714/0281 →
ASSIGNORS ASSIGNED 50% INTEREST Recorded Jan 10, 2011
From: FUJITSU LIMITED
To: FUJITSU LIMITED; TAIYO YUDEN CO., LTD.
Reel/Frame 025608/0733 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2006
From: MI, XIAOYU; MIZUNO, YOSHIHIRO; MATSUMOTO, TSUYOSHI; OKUDA, HISAO; UEDA, SATOSHI
To: FUJITSU LIMITED
Reel/Frame 018257/0805 →
Priority Claims (1)
JP 2005-252596 · Aug 31, 2005 · national
Continuity (1)
Related Publication 20070045773A1 · Mar 1, 2007