XFI-XAUI integrated circuit for use with 10GBASE-LX4 optical transceivers
View Patent ↗A single chip integrated circuit for use in an optical transceiver for converting and coupling an information containing electrical signal with an optical fiber having an XFI interface for coupling with an external electrical cable or information system device, and an XAUI interface for coupling with a laser transmitter subassembly including first, second, third and fourth lasers operating at different wavelengths and modulated by the respective four lane XAUI signals. The circuit includes an encoder for encoding the incoming XFI signal into four signals in the XAIU format, and a decoder coupled to the XAUI interface for receiving a four lane XAUI signal and converting it into a serial XFI signal coupled to the XFI interface.
1. A single chip integrated circuit for use in an optical transceiver for converting and coupling an information containing electrical signal with an optical fiber, comprising:
an XFI interface for exchanging data with an information system device;
an XAUI interface for exchanging data with a laser transmitter subassembly including first, second, third and fourth lasers operating at different wavelengths and modulated by a respective one of four lane XAUI signals and a receiver subassembly;
an encoder for encoding an incoming XFI serial signal from the information system device into four lane XAUI format for transmission by the laser transmitter subassembly;
a decoder coupled to said XAUI interface for receiving said four lane XAUI signals from said receiver subassembly, converting said four lane XAUI signals into a serial XFI signal and applying said serial XFI signal to the XFI interface for transmission to the information system device, wherein the XFI interface, the XAUI interface, the encoder and the decoder are included in the single chip integrated circuit;
lane synchronization and alignment circuits for each of the four lane XAUI signals coupled to the XAUI interface;
an 8B/10B decoder coupled to said lane synchronization and alignment circuits to produce unencoded received data;
a 64B/66B encoder for receiving unencoded received data and encoding it into a 64B/66B serial data stream; and
a first clock and data recovery circuit having an input coupled to the output of the 64B/66B encoder and an output coupled to the XFI interface.
2. A circuit as defined in claim 1 , further comprising a 64B/66B encoder for receiving unencoded received data and encoding it into a 64B/66B serial data stream.
3. A circuit as defined in claim 1 , further comprising a power down interface for placing the single chip integrated circuit in a low power mode with all functionality except the (I 2 C) interface disabled.
4. A circuit as defined in claim 1 , further comprising an inter-integrated circuit (I 2 C) interface for interfacing with the information system device as a slave.
5. A circuit as defined in claim 1 , further comprising a FIFO coupled between the decoder and the encoder.
6. A circuit as defined in claim 1 , further comprising an XFI equalizer.
7. A circuit as defined in claim 6 , further comprising a second clock and data recovery circuit having an input connected to the XFI equalizer and an output coupled to the 64B/66B encoder.
8. A circuit as defined in claim 1 , further comprising a Digital Optical Monitoring (DOM) circuit and a plurality of DOM registers.
9. A circuit as defined in claim 1 , further comprising an output pin for indicating the single chip integrated circuit has detected a condition that renders data invalid.
10. A circuit as defined in claim 1 , further comprising an output pin for indicating an operational fault or a status critical to the information system device.
11. A circuit as defined in claim 1 , further comprising an output pin for indicating insufficient optical power for reliable signal reception.