Digital power-on reset

1. An apparatus comprising:

a plurality of flip-flops each configured to (i) receive a clock signal and an input signal and (ii) generate an output signal, wherein said flip-flops are configured in series such that said output signal of a first of said flip-flops is presented as said input signal to a second of said flip-flops; and

a compare circuit configured to generate a reset signal in response to each of said output signals, wherein said reset signal is asserted until each of said output signals matches a set of predetermined values stored in said compare circuit.

2. The apparatus according to claim 1 , wherein (i) said reset signal remains asserted until said apparatus achieves a characteristic of a stable system and (ii) said characteristic occurs when each of said set of predetermined values stored in said compare circuit matches a corresponding one of said output signals.

3. The apparatus according to claim 1 , wherein said set of predetermined values comprises a steady-state pattern.

4. The apparatus according to claim 1 , wherein said clock signal oscillates at a fixed frequency.

5. The apparatus according to claim 1 , wherein a time that said reset signal remains asserted comprises a reset assertion time.

6. The apparatus according to claim 5 , wherein said reset assertion time is variable as a function to the number of flip-flops implemented.

7. The apparatus according to claim 1 , wherein said predetermined values comprise all zeros.

8. The apparatus according to claim 1 , wherein said predetermined values comprise all ones.

9. The apparatus according to claim 1 , wherein:

said plurality of flip-flops are divided into a first chain configured to generate a first set of said output signals and a second chain configured to generate a second set of said output signals; and

said compare circuit comprises (i) a first portion configured to generate a first compare signal by comparing said first set of said output signals to a predetermined value comprising all zeros, a second portion configured to generate a second compare signal by comparing said second set of outputs to a second predetermined value comprising all ones, and (iii) a gate circuit configured to generate said reset signal when both said first compare signal and said second compare signal are asserted.

10. An apparatus comprising:

a gate circuit configured to present a gated clock signal in response to a clock signal and an enable signal;

a plurality of flip-flops each configured to (i) receive said gated clock signal and an input signal and (ii) generate an output signal, wherein said flip-flops are configured in series such that said output signal of a first of said flip-flops is presented as said input signal to a second of said flip-flops; and

a compare circuit configured to generate a reset signal in response to each of said output signals, wherein (a) said reset signal is asserted if each of said output signals does not match a set of predetermined values stored in said compare circuit and (b) said reset signal is used as said enable signal for said gate circuit.

11. The apparatus according to claim 10 , wherein said reset signal remains asserted until said apparatus achieves a characteristic of a stable system.

12. The apparatus according to claim 11 , wherein said characteristic occurs when each of said set of predetermined values stored in said compare circuit matches a corresponding one of said output signals.

13. The apparatus according to claim 10 , wherein said set of predetermined values comprises a steady-state pattern.

14. The apparatus according to claim 10 , wherein said clock signal oscillates at a fixed frequency.

15. The apparatus according to claim 10 , wherein a time that said reset signal remains asserted comprises a reset assertion time.

16. The apparatus according to claim 15 , wherein said reset assertion time is variable as a function to the number of flip-flops implemented.