Testing apparatus and testing method

1. A testing apparatus for testing a memory under test, comprising:

a pattern generator for generating an address signal and a data signal to be provided to the memory under test, and an expected value signal indicating an expected value that the memory under test outputs in a normal state, according to the address signal and the data signal;

a logic comparator for comparing an output signal outputted by the memory under test according to the address signal and the data signal with the expected value signal and outputting fail data when the output signal is not matched with the expected value signal, the fail data comprising a first fail data from a first test of the memory under test, a second fail data from a second test of the memory under test, and a third fail data from a third test of the memory under test;

a first fail buffer memory for storing the first fail data on an address indicated by the address signal;

a second fail buffer memory for accumulating the first fail data stored in the first fail buffer memory and the second fail data and storing the first and second fail data;

a fail data transmitting section for receiving the fail data from the logic comparator and one of the fail data stored in the first fail buffer memory and the fail data stored in the second fail buffer memory, performing an operation based on the received fail data, and providing a result of the operation to the first fail buffer memory or the second fail buffer memory; and

a first safe analysis section for performing a fail safe analysis on the memory under test with reference to the first fail data stored in the first fail buffer memory,

wherein

the first fail buffer memory accumulates the first and second fail data stored in the second fail buffer memory and the third fail data and stores the first second and third fail data, and

the first safe analysis section performs a fail safe analysis on the memory under test further with reference to the first and second fail data stored in the second fail buffer memory.

2. The testing apparatus according to claim 1 further comprising an OR circuit for performing an OR operation on the second fail data and the fail data stored in the first fail buffer memory and storing the result in the second fail buffer memory, and for performing an OR operation on the third fail data and the fail data stored in the second fail buffer memory and storing the result in the first fail buffer memory.

3. The testing apparatus according to claim 2 further comprising a first address fail memory for storing sequentialty the first fail data outputted by the logic comparator on the address indicated by the address signal, wherein

the first fail buffer memory accumulates and stores the fail data stored in the first address fail memory and the fail data stored in the second fail buffer memory, and

the second fail buffer memory accumulates and stores the fail data stored in the first address fail memory and the fail data stored in the first fail buffer memory.

4. The testing apparatus according to claim 3 further comprising a second address fail memory for storing sequentially the second fail data outputted by the logic comparator on the address indicated by the address signal, wherein

the second fail buffer memory accumulates and stores the fail data stored in the first fail buffer memory and the fail data stored in the second address fail memory in parallel with performing the third test of the memory under test.

5. The testing apparatus according to claim 4 , wherein

the first address fail memory sequentially stores therein the third fail data outputted by the logic comparator on the address indicated by the address signal, and

the first fail buffer memory accumulates and stores the fail data stored in the second fail buffer memory and the fail data stored in the first address fail memory in parallel with performing a fourth test of the memory under test.

6. The testing apparatus according to claim 5 further comprising a delay circuit for delaying the fail data stored in the first address fail memory or the second address fail memory in order to match the timing at which the fail data stored in the first address fail memory or the second address fail memory is provided to the OR circuit with the timing at which the fail data stored in the first fail buffer memory or the second fail buffer memory is provided to the OR circuit and providing the delayed fail data to the OR circuit.

7. The testing apparatus according to claim 1 further comprising:

a third fail buffer memory for storing in parallel with the first fail buffer memory or the second fail buffer memory fail data that is the same as the fail data provided to the first fail buffer memory or the second fail buffer memory; and

a second safe analysis section for performing in parallel with the first safe analysis section a fail safe analysis on the memory under test with reference to the fail data stored in the third fail buffer memory.

8. The testing apparatus according to claim 1 further comprising a third safe analysis section for performing in parallel with the first safe analysis section a fail safe analysis of the memory under test with reference to the first fail data stored in the first fail buffer memory.

9. A testing method for testing a memory under test, comprising:

providing an address signal and a data signal to the memory under test;

comparing an output signal outputted by the memory under test according to the address signal and the data signal with an expected value signal indicating an expected value that the memory under test outputs in a normal state according to the address signal and the data signal, and generating fail data when the output signal in not matched with the expected value signal, the fail data comprising a first fail data from a first test of the memory under test, a second fail data from a second test of the memory under test, and a third fail data from a third test of the memory under test;

storing sequentially the first fail data on an address in a first address fail memory indicated by the address signal in parallel with performing a first test of the memory under test;

storing sequentially the second fail data on an address in a second address fail memory indicated by the address signal in parallel with performing a second test of the memory under test;

reading the fail data stored in the first address fail memory to a first fail buffer memory in parallel with performing the second test, and performing a fail safe analysis on the memory under test with reference to the fail data stored in the first fail buffer memory;

storing sequentially the third fail data on the address in the first address fail memory indicated by the address signal in parallel with performing a third test of the memory under test;

accumulating and storing in a second fail buffer memory the fail data stored in the first fail buffer memory and the fail data stored in the second address fail memory in parallel with performing the third test, and performing a fail safe analysis on the memory under test with reference to the first and second fail data stored in the second fail buffer memory; and

receiving the generated fail data and one of the fail data stored in the first fail buffer memory and the fail data stored in the second fail buffer memory, performing an operation based on the received data, and providing a result of the operation to the first fail buffer memory or the second fail buffer memory.