Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
View Patent ↗A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the first bits and a bit of the N-order of the second bits are stored in one of the cells, the N being an integral number. A voltage corresponding to the N-order bits is generated and applied to the one of the cells in response to an address information corresponding thereto. Another semiconductor device has multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2 n levels of data each expressed by n (n≧2) number of bits (X 1 , X 2 , . . . , Xn). A logical address is converted into a physical address of the physical address space. Judging is made whether a logical address space including the logical address matches the physical address space. When matched, the most significant bit X 1 is specified once using a reference value. The specified bit is output from one of the cells corresponding to the physical address. If not matched, the bits (X 2 , . . . , Xn) are specified by n—time specifying operation maximum using maximum n number of different reference values. The data writing/reading operations to/from the semiconductor devices can be stored in a computer readable medium as program codes for causing a computer to execute these operations.
1. A memory device comprising:
a plurality of multilevel memory cells, wherein each of the memory cells is configured to store a voltage level that represents at least two bits of data; and
memory control circuitry configured to control the reading of the plurality of memory cells in response to received read requests, wherein the memory control circuitry is configured to read a first set of selected cells by performing a single voltage comparison operation in response to a first read request specifying a first address, and to read a second set of selected cells by performing multiple voltage comparison operations in response to a second read request specifying a second address.
2. The memory device as recited in claim 1 wherein the memory control circuitry is configured to read data corresponding to the first address by determining whether a level stored by each cell of the first set of selected memory cells is above or below a median threshold value.
3. The memory device as recited in claim 1 wherein the memory control circuitry is configured to read data by performing a single voltage comparison operation in response to any read request corresponding to a first range of address values, and to read data by performing multiple voltage comparison operations in response to any read request corresponding to a second range of address values.
4. The memory device as recited in claim 3 wherein the highest order bit of a given address value is used to delineate the first range address values from the second range of address values.
5. The memory device as recited in claim 3 wherein the first range of address values specifies physical addresses.
6. The memory device as recited in claim 1 wherein each of the memory cells is configured to store any one of four voltage levels to thereby represent two bits.
7. The memory device as recited in claim 6 wherein the memory control circuitry is configured read the first set of selected cells by determining whether a level stored by each the first set of selected cells is above or below a median of the lowest of the voltage levels and the highest of the voltage levels.
8. The memory device as recited in claim 7 wherein the memory control circuitry is configured to read the second set of selected cells by performing multiple voltage comparison operations to determine which one of the four voltage levels is stored by each of the second set of selected cells.
9. The memory device as recited in claim 1 wherein each of the memory cells is configured to store any one of eight voltage levels to thereby represent three bits.
10. A system comprising:
a memory device; and
a computer operable to activate the memory device, wherein the memory device includes:
a plurality of multilevel memory cells, wherein each of the memory cells is configured to store a voltage level that represents at least two bits of data; and
memory control circuitry configured to control the reading of the plurality of memory cells in response to received read requests, wherein the memory control circuitry is configured to read a first set of selected cells by performing a single voltage comparison operation in response to a first read request specifying a first address, and to read a second set of selected cells by performing multiple voltage comparison operations in response to a second read request specifying a second address.
11. The system as recited in claim 10 wherein the memory control circuitry is configured to read data corresponding to the first address by determining whether a level stored by each cell of the first set of selected memory cells is above or below a median threshold value.
12. The system as recited in claim 10 wherein the memory control circuitry is configured to read data by performing a single voltage comparison operation in response to any read request corresponding to a first range of address values, and to read data by performing multiple voltage comparison operations in response to any read request corresponding to a second range of address values.
13. The system as recited in claim 12 wherein the highest order bit of a given address value is used to delineate the first range address values from the second range of address values.
14. The system as recited in claim 10 wherein each of the memory cells is configured to store any one of four voltage levels to thereby represent two bits.
15. The system as recited in claim 14 wherein the memory control circuitry is configured read the first set of selected cells by determining whether a level stored by each the first set of selected cells is above or below a median of the lowest of the voltage levels and the highest of the voltage levels.
16. The system as recited in claim 10 wherein each of the plurality of multilevel memory cells is a floating gate type memory cell.
17. The system as recited in claim 10 wherein each of the plurality of multilevel memory cells is an MNOS type memory cell.
18. A method of reading data in a memory device including a plurality of multilevel memory cells, wherein each of the memory cells is configured to store a value that represents at least two bits, the method comprising:
reading a first set of selected cells by performing a single voltage comparison operation in response to a first read request specifying a first address; and
reading a second set of selected cells by performing multiple voltage comparison operations in response to a second read request specifying a second address.
19. The method as recited in claim 18 wherein reading data corresponding to the first address is performed by determining whether a level stored by each cell of the first set of selected memory cells is above or below a median threshold value.
20. The method as recited in claim 18 further comprising reading data by performing a single voltage comparison operation in response to any read request corresponding to a first range of address values, and reading data by performing multiple voltage comparison operations in response to any read request corresponding to a second range of address values.
21. The method as recited in claim 20 wherein the highest order bit of a given address value is used to delineate the first range address values from the second range of address values.
22. The method as recited in claim 18 wherein each of the memory cells is configured to store any one of four voltage levels to thereby represent two bits.
23. The method as recited in claim 22 wherein reading the first set of selected cells is performed by determining whether a level stored by each the first set of selected cells is above or below a median of the lowest of the voltage levels and the highest of the voltage levels.
24. The method as recited in claim 23 wherein the second set of selected cells is read by performing multiple voltage comparison operations to determine which one of the four voltage levels is stored by each of the second set of selected cells.
25. The method as recited in claim 18 wherein each of the plurality of multilevel memory cells is electrically erasable and progranunable.