IC package with a protective encapsulant and a stiffening encapsulant
An IC package mainly includes a substrate having slot(s), a chip, a protective encapsulant, a stiffening encapsulant, and a plurality of external terminals. The Young's modulus of the stiffening encapsulant is greater than the one of the protective encapsulant and the curing shrinkage of the stiffening encapsulant is smaller than the one of the protective encapsulant. The protective encapsulant is formed on one of the surfaces of the substrate for encapsulating the chip. The stiffening encapsulant protrudes from the other surface of the substrate where the external terminals are disposed. Moreover, the stiffening encapsulant is formed inside the slot and is contacted with the chip. Since the stiffening encapsulant is embedded and formed inside the slot, therefore, the contact area of the stiffening encapsulant with the substrate is increased to enhance the warpage resistance of the IC package.
1. An IC package comprising:
a substrate having a top surface, a bottom surface and at least a slot;
a chip disposed on the top surface of the substrate and having an active surface partially exposed from the slot;
a protective encapsulant formed on the top surface of the substrate and at least encapsulating the sides of the chip;
at least a stiffening encapsulant having a Young's modulus greater than the one of the protective encapsulant and having a curing shrinkage smaller than the one of the protective encapsulant, wherein the stiffening encapsulant is in a strip and is formed inside the slot to contact with the exposed active surface of the chip and protrudes from the bottom surface of the substrate; and
a plurality of external terminals disposed on the bottom surface of the substrate,
wherein the substrate has a plurality of top molding gates on the top surface and a bottom molding gate on the bottom surface, wherein the bottom molding gate is not aligned with the top molding gates.
2. The IC package of claim 1 , wherein the stiffening encapsulant has a cross section of a reverse “T”.
3. The IC package of claim 1 , wherein the Young's modulus of the stiffening encapsulant is between 20 GPa and 50 GPa and the curing shrinkage of the stiffening encapsulant is between 0.01% and 0.1%.
4. The IC package of claim 1 , wherein a long central axis is defined on the substrate, wherein the slot is formed on the long central axis and is shorter than one of sides of the chip parallel to the long central axis.
5. The IC package of claim 1 , wherein the area of the active surface of the chip is not less than 70% of the one of the top surface of the substrate so that the IC package is a Chip Scale Package (CSP).
6. The IC package of claim 1 , wherein the top molding gates are symmetrically disposed on both sides of the bottom molding gate.
7. The IC package of claim 1 , further comprising a plurality of bonding wires passing through the slot to electrically connect the chip to the substrate and encapsulated by the stiffening encapsulant.