Semiconductor memory device having a floating gate
View Patent ↗To prevent the extraction of electrons from the floating gate during a read operation. A semiconductor memory device comprises a selection gate 3 a provided in a first region on a substrate 1 through an insulating film 2 , a floating gate 6 a provided in a second region adjacent to the first region through an insulating film 5 , a first and second diffusion regions 7 a and 7 b provided in a third region adjacent to the second region, and a control gate 11 provided over the floating gate 6 a through an insulating film 8 , the control gate 11 intersects with the selection gate 3 a at different levels, a third diffusion region 21 is provided in a fourth region located near an extending part of the selection gate 3 a on the surface of the substrate, the floating gate 6 a is formed in the form of a side wall, and it has a round part 6 b at the top on the side directed to the side wall surface of the selection gate 3 a.
1. A semiconductor memory device comprising:
a selection gate provided in a first region on a substrate;
a floating gate provided in a second region adjacent to said first region;
first and second diffusion regions provided in a third region adjacent to said second region; and
a control gate provided over said floating gate and a part of said selection gate,
wherein said floating gate is formed in a side wall form on a side wall surface of the selection gate and comprises a round part formed adjacent to said control gate.
2. The semiconductor memory device as defined in claim 1 , wherein said round part is on a side directed to a side wall surface of said selection gate.
3. The semiconductor memory device as defined in claim 1 , wherein a pair of floating gates are provided in a pair of second regions adjacent to said first region,
wherein said first diffusion region and said second diffusion regions are provided in a pair of third regions adjacent to said second regions, respectively, and
wherein said control gate is provided over said pair of floating gates, each of which comprises a round part at the top of said floating gates.
4. The semiconductor memory device as defined in claim 1 , further comprising:
an insulating layer that insulates said floating gate from the substrate and the selection gate.
5. The semiconductor memory device as defined in claim 1 , wherein said round part comprises a curvature radius not less than 10 nm.
6. The semiconductor memory device as defined in claim 1 , wherein said round part is formed on a side of said floating gate that faces said control gate.
7. The semiconductor memory device as defined in claim 1 , further comprising:
a selection gate insulating film formed between said substrate and said selection gate.
8. The semiconductor memory device as defined in claim 7 , further comprising:
a first insulating film formed on said selection gate, and a second insulating film formed on said first insulating film.
9. The semiconductor memory device as defined in claim 8 , further comprising:
a third insulating film formed on said second insulating film and between said round part and said control gate.
10. The semiconductor memory device as defined in claim 9 , further comprising:
a tunnel insulating film formed between said floating gate, and a side wall of said selection gate, said first insulating film and said second insulating film.
11. The semiconductor memory device as defined in claim 1 , wherein said selection gate comprises a plurality of comb tooth-shaped portions.
12. The semiconductor memory device as defined in claim 11 , wherein said comb tooth-shaped portions of said selection gate are interlocked with comb tooth-shaped portions of another selection gate.
13. The semiconductor memory device as defined in claim 12 , wherein said first and second diffusion regions are disposed along a direction in which said comb tooth-shaped portions extend, and
wherein said first and second diffusion regions comprise a drain region during a write operation and a source region during a read operation.
14. The semiconductor memory device as defined in claim 11 , wherein said control gate extends in a direction perpendicular to said comb tooth-shaped portions, and controls a channel in a region between said selection gate and said first diffusion region.
15. The semiconductor memory device as defined in claim 1 , wherein said round part inhibits an extraction of electrons from said floating gate during a read operation.
16. A semiconductor memory device comprising:
a selection gate provided in a first region on a substrate;
a floating gate provided in a second region adjacent to said first region;
first and second diffusion regions provided in a third region adjacent to said second region; and
a control gate provided over said floating gate,
wherein said floating gate is formed in a side wall form and comprises a round part formed adjacent to said control gate and on the side directed to a side wall surface of said selection gate.
17. The semiconductor memory device as defined in claim 16 , wherein a pair of floating gates are provided in a pair of second regions adjacent to said first region,
wherein said first diffusion region and said second diffusion regions being provided in a pair of third regions adjacent to said second regions, respectively, and
wherein said control gate is provided over said pair of floating gates, each of which comprises a round part at the top of said floating gates.
18. The semiconductor memory device as defined in claim 16 , further comprising: an insulating layer that insulates said floating gate from the substrate and the selection gate.
19. The semiconductor memory device as defined in claim 16 , wherein said round part comprises a curvature radius not less than 10 nm.