Semiconductor memory device with no latch error

1. A dynamic random access memory (DRAM) comprising:

a data signal input circuit configured to input a data signal in response to a data control signal;

a data strobe signal input circuit configured to input a data strobe signal in response to a data strobe control signal;

a control circuit configured to separately generate said data control signal and said data strobe control signal;

a data latch circuit configured to latch said data signal from said data signal input circuit in response to said data strobe signal from said data strobe signal input circuit;

a memory cell array having a plurality of memory cells arranged in a matrix, wherein said latched data signal is stored in a selected one of said plurality of memory cells through said data buffer;

an amplifier circuit configured to amplify a data signal read out from said selected memory cell; and

an output circuit configured to output the amplified data signal.

2. The DRAM according to claim 1 , wherein said control circuit generates said data strobe control signal to deactivate said data strobe signal input circuit before said data strobe signal inputted to said data strobe signal input circuit is set to a state other than high and low states.

3. The DRAM according to claim 1 , wherein said data control signal and said data strobe control signal are independent from each other at timing.

4. The DRAM according to claim 1 , wherein said control circuit comprises:

a write control circuit configured to generate first and second signals from an internal clock signal which is synchronized with an external clock signal, a write command signal and a mode signal specifying an operation mode;

a first circuit configured to generate said data control signal from said first and second signals; and

a second circuit configured to generate said data control signal from said first signal in response to an inversion signal of said data strobe signal.

5. The DRAM according to claim 4 , wherein said second circuit comprises:

a D-type flip-flop circuit configured to latch said first signal in resynchronization with an inversion signal of said internal clock signal to generate a third signal;

a D-type latch circuit configured to pass said third signal in response to said data strobe signal to generate said strobe control signal; and

an OR circuit configured to output a logical summation of said first signal and the passed third signal.

6. The DRAM according to claim 4 , wherein said mode signal is generated by an operation mode setting circuit based on an input command and indicates a number of data on said data signal.

7. The DRAM according to claim 4 , wherein said mode signal is generated based on a number of data on said data signal and a number of clock periods from said writing command signal to output of said data signal.

8. The DRAM according to claim 1 , wherein said data strobe signal input circuit further comprises:

a delay circuit configured to delay said data strobe signal, and

said data strobe signal supplied to said data latch circuit is said delayed data strobe signal.

9. An input control circuit comprising:

a write control circuit configured to generate first and second signals from an internal clock signal which is synchronized with an external clock signal, a write command signal and a mode signal specifying an operation mode;

a first latch circuit configured to latch said first signal in synchronization with a falling edge of an external clock signal; and

a second latch circuit configured to pass an output signal of said first latch circuit for a period during which an output signal of a data strobe circuit is in a low level,

wherein said second latch circuit switches said data strobe circuit from a active state to a inactive state in response to an output signal of said second latch circuit.

10. The input control circuit according to claim 9 , wherein said second latch circuit switches a falling edge of the output signal of said second latch circuit at a timing delayed for a period by which a write command is delayed.

11. An input control method comprising:

inputting a data signal in response to a data control signal;

inputting a data strobe signal in response to a data strobe control signal;

latching said data signal in response to said data strobe signal; and

separately generating said data control signal and said data strobe control signal.

12. The input control method according to claim 11 , wherein said separately generating comprises:

generating said data strobe control signal; and

setting a generation timing of said data strobe control signal in response to an internal clock signal associated with a low level period of said data strobe signal after the last data on said data signal.

13. The input control method according to claim 11 , wherein said separately generating comprises:

generating a first signal by counting an internal signal synchronized with the rising edge of an external clock signal, from a write command signal for an active stated of a preset signal;

generating a second signal by latching said first signal in response to an internal signal synchronized with a falling edge of an external clock signal; and

passing said second signal in response to an internal data strobe signal corresponding to a low level period of said data strobe signal.

14. The input control method according to claim 12 , wherein said preset signal is a signal indicative of a number of said data.

15. The input control method according to claim 12 , wherein said preset signal is a signal indicative of a number of the data on said data signal and a number of clock cycles in a period from said write command signal to said data signal.

16. The input control method according to claim 12 , further comprising:

using a first output signal of said data strobe circuit to which a data strobe signal passing through a delay circuit is supplied for a data latch circuit; and

using a second output signal of said data strobe circuit which does not pass said delay circuit for a control circuit.