Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafer
View Patent ↗Epitaxially coated silicon wafers, are coated individually in an epitaxy reactor by placing a wafer on a susceptor, pretreating under a hydrogen atmosphere, in and then with addition of an etching medium, and coating epitaxially on a polished front side, wherein an etching treatment of the susceptor is effected after a specific number of epitaxial coatings, and the susceptor is then hydrophilized. Silicon wafer produced thereby have a maximum local flatness value SFQR max of 0.01 μm to 0.035 μm relative to at least 99% of the partial regions of an area grid of measurement windows having a size of 26×8 mm 2 on the front side of the silicon wafer with an edge exclusion of 2 mm.
1. A method for producing epitaxially coated silicon wafers, in which a multiplicity of silicon wafers having a front side and a rear side are polished at least on a front side thereof, comprising successively and individually coating said wafers in an epitaxy reactor, wherein one silicon wafer is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere in a first step, and with addition of an etching medium to the hydrogen in a second step, is subsequently coated epitaxially on its polished front side, and is removed from the epitaxy reactor, wherein an etching treatment of the susceptor is effected after a specific number of epitaxial coatings, and the susceptor is hydrophilized after said etching treatment, wherein the silicon wafers have a front side and a rear side, at least the front sides being polished, and an epitaxial layer applied at least the front sides, the wafers having a maximum local flatness value SFQR max of 0.01 μm to 0.035 μm relative to at least 99% of the partial regions of an area grid of measurement windows having a size of 26×8 mm 2 on the front sides of the coated silicon wafers, with an edge exclusion of 2 mm, having a maximum local flatness value SFQR max of 0.01 μm to 0.035 μm relative to at least 99% of the partial regions of an area grid of measurement windows having a size of 26×8 mm 2 on the front side of the coated silicon wafer with an edge exclusion of 2 mm.
2. The method of claim 1 , wherein the susceptor is hydrophilized by momentarily placing a hydrophilic wafer onto the susceptor and subsequently removing said wafer from the epitaxy reactor.
3. The method of claim 2 , wherein an etching treatment of the susceptor is effected after each epitaxial coating.
4. The method of claim 2 , wherein the hydrophilic wafer is placed onto the susceptor for 1-30-seconds at a temperature in the range of 700-1100°C.
5. The method of claim 2 , wherein the hydrophilic wafer is a silicon wafer and a hydrophilic layer on the silicon wafer is a thermal oxide layer.
6. The method of claim 5 , wherein the thermal oxide layer of silicon wafer is placed onto the susceptor for 1-10 seconds, at a temperature in the range of 700-900°C.
7. The method of claim 2 , wherein the hydrophilic wafer is used more than once.
8. The method of claim 1 , wherein an etching treatment of the susceptor is effected after each epitaxial coating.
9. The method of claim 1 , wherein a silicon layer is deposited on the susceptor after the etching treatment of the susceptor.
10. The method of claim 1 , wherein the silicon wafers are polished by means of DSP on the front side and rear side.
11. The method of claim 1 , wherein the silicon wafers are polished by means of CMP on their front side.
12. The method of claim 1 , wherein a susceptor with a polished bearing area is used.
13. The method of claim 1 , wherein the silicon wafers are wafers made of monocrystalline silicon, SOI wafers, wafers having a strained silicon layer, or sSOI wafers.
14. A silicon wafer having a front side and a rear side, at least its front side being polished and an epitaxial layer applied at least its front side, having a maximum local flatness value SFQR max of 0.01 μm to 0.035 μm relative to at least 99% of the partial regions of an area grid of measurement windows having a size of 26×8 mm 2 on the front side of the coated silicon wafer with an edge exclusion of 2 mm.
15. The silicon wafer of claim 14 , comprising polished front and rear sides, a CMP-polished front side and an epitaxial layer on the front side, the front side having a maximum local flatness value SFQR max of 0.01 μm to 0.025 μm.
16. The silicon wafer of claim 15 , the front and rear sides thereof polished by DSP.
17. The silicon wafer of claim 14 , having a maximum local flatness value SFQR max of 0.01 μm to 0.02 μm, relative to all the partial regions of an area grid of measurement windows having a size of 26×8 mm 2 on the front side of the coated silicon wafer.
18. The silicon wafer of claim 14 , where the silicon wafer, prior to being provided with an epitaxial layer, is selected from the group consisting of wafers made of monocrystalline silicon, SOI wafers, wafers with a strained silicon layer, and a sSOI wafers.
19. The silicon wafer of claim 14 , the thickness of the epitaxial layer applied on its front side is 0.5-5 μm in thickness.